A described example includes: a semiconductor die including a Hall sensor arranged in a first plane that is parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed over the device side surface of the semiconductor die, the upper surface of the magnetic alloy layer covered by a layer of polymer material; a backside surface of the semiconductor die opposite the device side surface mounted to a die side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device side surface spaced from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and the die side surface of the die pad.

A semiconductor memory device includes first and second word lines, a bit line, a source line, and a memory cell. The memory cell includes a spin-orbit torque (SOT) pattern having a first end electrically coupled to the source line, a magnetic tunnel junction pattern extending adjacent the SOT pattern, and a read transistor having a first current carrying terminal electrically coupled to a first end of the magnetic tunnel junction pattern, a second current carrying terminal electrically coupled to the bit line, and a gate terminal electrically coupled to the first word line. The memory cell also includes a write transistor having a first current carrying terminal electrically coupled to a second end of the SOT pattern, a second current carrying terminal electrically coupled to the first end of the magnetic tunnel junction pattern, and a gate terminal electrically coupled to the second word line.

A magnetic recording array according to the present embodiment includes a plurality of spin elements, a first reference cell, and a second reference cell, wherein the plurality of spin elements, the first reference cell, and the second reference cell each have a wiring and a stacked body including a first ferromagnetic layer stacked on the wiring, wherein the electrical resistance of the wiring of the first reference cell is higher than the electrical resistance of the wiring of each spin element, and wherein the electrical resistance of the wiring of the second reference cell is lower than the electrical resistance of the wiring of each spin element.

Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

A ferromagnetic laminated film includes a plurality of first magnetic layers, at least one second magnetic layer, and at least one first non-magnetic layer, in which the first magnetic layers are alternately laminated with the second magnetic layer or the first non-magnetic layer, and a material forming the first magnetic layers is different from a material forming the second magnetic layer, and the first magnetic layers, the first non-magnetic layer, and the second magnetic layer are a material combination in which interface magnetic anisotropy is generated between the first magnetic layer and the first non-magnetic layer, and a material combination in which interface magnetic anisotropy is generated between the first magnetic layer and the second magnetic layer.

A Hall sensor structure comprising a semiconductor body of a first conductivity type, a well region of a second conductivity type extending from a top side of the semiconductor body into the semiconductor body, at least three first semiconductor contact regions of the second conductivity type, each extending from a top side of the well region into the well region, at least one second semiconductor contact region of a second conductivity type, wherein the first semiconductor contact regions are spaced apart from one another and from an edge of the well region, a metallic connection contact layer is arranged on each first semiconductor contact region, the at least one second semiconductor contact region extends along the top side of the semiconductor body at least partially around the well region.

A magnetic sensor includes a magneto-sensitive portion (105); an excitation wiring (110) formed in a wiring region above the magneto-sensitive portion (105) through intermediation of an insulating film (12), the excitation wiring (110) including a plurality of conductor portions (1101, 1102, 1103, 1104, and 1105) arranged in in order across at least one radial direction from a center axis of the magneto-sensitive portion (105); a current flowing through the excitation wiring (110) having a current density of which an absolute value becomes zero in a vicinity of a center of the magneto-sensitive portion (105) and continuously increases toward an outer side of the magneto-sensitive portion (105); and a magnetic field generated by the current flowing through the excitation wiring (110) in a direction vertical to the surface of the magneto-sensitive portion (105).

Disclosed are a synthetic antiferromagnetic material using the Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction and a multibit memory using the synthetic antiferromagnetic material that is formed. The synthetic antiferromagnetic material has a non-magnetic metal layer as an RKKY inducing layer in the center, interaction between upper and lower ferromagnetic layers is imparted according to the thickness of the RKKY inducing layer, and the magnetization of an anti-parallel state is maximized therebetween. When such synthetic antiferromagnetic materials are cumulatively stacked and tunnel barrier layers are provided therebetween, multiple bits can be stored. Namely, data may be stored by supplying a program current in parallel to the surface of the RKKY inducing layer, and a resistance state may be checked by supplying current in a vertical direction to the surface of the RKKY inducing layer.

The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

According to one embodiment, an arithmetic device includes an arithmetic element part, and a controller. The arithmetic element part includes first and second elements. The first element includes a first conductive member and a first stacked body. The first conductive member includes first to third portions. The first stacked body includes a first magnetic layer, and a first counter magnetic layer. The second element includes a second conductive member and a second stacked body. The second conductive member includes fourth and fifth portions, and a sixth portion between the fourth and fifth portions. The second stacked body includes a second magnetic layer, and a second counter magnetic layer. The controller is configured to perform an XNOR operation of first and second inputs. The first input corresponds to electrical resistances of the stacked bodies. The second input corresponds to potentials of the magnetic layers.