A magnetic recording array includes a plurality of units. Each unit has a first magnetoresistance effect element, second magnetoresistance effect element, and writing transistor. Each of the first magnetoresistance effect element and the second magnetoresistance effect element has a wiring and a laminate which is laminated on the wiring. The writing transistor is connected to each of the wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element. The wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element are electrically connected in series at the time of writing, and a writing current flows through each of the wirings. A direction of a writing current flowing in the wiring of the first magnetoresistance effect element and a direction of a writing current flowing in the wiring of the second magnetoresistance effect element are opposite to each other.

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

A semiconductor memory device has a first wiring extending in a first direction and a second wiring extending in a second direction. The first and second wirings are spaced from each other in a third direction. The second wiring has a first recess facing the first wiring. A resistance change memory element is connected between the first and second wirings. A conductive layer is between the resistance change memory element and the second wiring and includes a first protrusion facing the second wiring. A switching portion is between the conductive layer and the second wiring and includes a second recess facing the conductive layer and a second protrusion facing the second wiring. The first protrusion is in the second recess. The second protrusion is in the first recess. The switching portion is configured to switch conductivity state according to voltage between the first wiring and the second wiring.

A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.

A tunnel magnetoresistance effect (TMR) device includes an exchange coupling film having a first ferromagnetic layer, which is at least a portion of a fixed magnetic layer, and an antiferromagnetic layer laminated on the first ferromagnetic layer. The ferromagnetic layer includes an X(Cr—Mn) layer containing one or two or more elements X selected from the group consisting of the platinum group elements and Ni, and also containing Mn and Cr. The X(Cr—Mn) layer has a first region relatively near the first ferromagnetic layer, and a second region relatively far away from the first ferromagnetic layer, and the content of Mn in the first region is higher than that in the second region.

An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.

A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.

According to one embodiment, a magnetoresistive memory device includes: a first conductor; a layer stack; an insulator on a side surface of the layer stack; a second conductor on a second surface of the layer stack; a third conductor; and a fourth conductor on the third conductor. The layer stack includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer and has a first surface in contact with the first conductor. The second surface is at an opposite side of the first surface. The third conductor has a portion on the second conductor and a portion on a side surface of the insulator.