Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a metallic barrier liner containing an intermetallic compound of at least two elements that includes a first metal element including Ta or Ti, and a second metal element including at least one of Al or Mo, and metallic barrier liner containing less than 10 atomic percent of nitrogen and oxygen, and a metallic fill material layer contacting the metallic barrier liner.

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures located within a respective memory opening vertically extending through the alternating stack in a memory array region, and support pillar structures vertically extending through the alternating stack. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective memory film that contacts each layer within the alternating stack. Each of the support pillar structures includes a respective dummy vertical semiconductor channel, a respective dummy memory film, and at least one respective dielectric spacer material portion laterally surrounding the respective dummy memory film and interposed between the electrically conductive layers and the respective dummy memory film.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory opening fill structures including a respective vertical semiconductor channel and a respective memory film, and support pillar structures including a respective dummy vertical semiconductor channel, a respective dummy memory film, and a vertical stack of dielectric spacer fins located at levels of the electrically conductive layers and interposed between the electrically conductive layers and the respective dummy memory film.

Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.

A semiconductor device includes a substrate and a first semiconductor layer and a second semiconductor layer each extending in a first direction perpendicular to a surface of the substrate. Furthermore, the semiconductor device includes a first plug provided on the first semiconductor layer and a second plug provided on the second semiconductor layers, and a connection wiring having an upper surface that is at a same height along the first direction as upper surfaces of the first and second plugs, and having a lower surface that is at a same height along the first direction as lower surfaces of the first and second plugs. Furthermore, the semiconductor device includes a first wiring provided on the first plug and the connection wiring and a second wiring provided on the second plug and the connection wiring.

A method of manufacturing a semiconductor device includes: forming a first stack structure; forming first holes penetrating the first stack structure; forming a second stack structure on the first stack structure; forming second holes penetrating the second stack structure; measuring first direction distances between edges of the first holes and edges of the second holes; and correcting a first direction position at which the second holes are to be formed. The second holes may include one of a first shift hole shifted in a positive first direction from a first hole and a second shift hole shifted in a negative first direction from a first hole.

A semiconductor memory device includes an electrode structure including a plurality of gate conductive films stacked on a substrate and a channel array in which a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns may include a first column whose uppermost plane has a first shape and a second column whose uppermost plane has a second shape. N (N is a natural number equal to more than 1) first columns and N second columns are alternately arranged in a first direction different from the second direction.

A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.