A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

A memory die includes source-select-level electrically conductive strips laterally spaced apart by source-select-level dielectric isolation structures, an alternating stack of word-line-level electrically conductive layers and insulating layers; and source strips located on an opposite side of the source-select-level electrically conductive strips. Each of the source strips has an areal overlap with only a respective one of the source-select-level electrically conductive strips. Memory stack structures vertically extend through the alternating stack and a respective subset of the source-select-level electrically conductive strips. A logic die may be bonded to the memory die on an opposite side of the source strips. Each source strip is electrically connected to a respective group of memory stack structures laterally surrounded by a respective source-select-level electrically conductive strip.

A semiconductor device and data storage system, the device including a substrate having a first region, a second region surrounding the first region, and a third region surrounding the second region; a memory structure on the first region; a first defect detector on the second region; and a dam structure on the third region, wherein the dam structure surrounds the first defect detector and includes a plurality of conductive lines stacked on the third region.

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2).sup.th batch of program data, N being an integer equal to or greater than 2, program an (N−1).sup.th batch of program data into respective pages in the 3D NAND memory array, and cache an N.sup.th batch of program data in respective space in the on-die cache as a backup copy of the N.sup.th batch of program data.

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Each memory stack structure includes a memory film and a vertical semiconductor channel. A sacrificial polycrystalline metal layer may be formed on each memory film, and a carbon precursor may be decomposed on a physically exposed surface of the sacrificial polycrystalline metal layer to generate adsorbed carbon atoms. A subset of the adsorbed carbon atoms diffuses through grain boundaries in the polycrystalline e metal layer to an interface with the memory film. The carbon atoms at the interface may be coalesced into at least one graphene layer by an anneal process. The at least one graphene layer functions as a vertical semiconductor channel, which provides a higher mobility than silicon. A metallic drain region may be formed at an upper end of each vertical semiconductor channel.

A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).