Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a substrate with a complementary metal oxide semiconductor (CMOS) circuit; a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked on the substrate in a vertical direction; a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and a plurality of conductive layers disposed over the gate stacked body. Each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.

A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1.sup.st cell and a 2.sup.nd cell placed next to each other in a cell width direction, wherein the 1.sup.st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1.sup.st cell, and connects a vertical field-effect transistor (VFET) of the 1.sup.st cell to a power rail of the 1.sup.st cell, wherein a 2.sup.nd cell includes a connector connected to a power rail of the 2.sup.nd cell, wherein the fin of the 1.sup.st cell and the connector of the 2.sup.nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1.sup.st cell and the connector of the 2.sup.nd cell are merged.

There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.

A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack including interlayer insulating layers and word lines alternately stacked in a first direction, channel pillars passing through the gate stack and tapering toward the first direction, source select lines surrounding the channel pillars and extending to overlap the gate stack, and a source isolation insulating layer overlapping the gate stack between the source select lines and tapering toward a direction opposite to the first direction.

An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

A semiconductor device includes a lower circuit structure including a lower conductive pattern on a substrate, a middle wiring structure including horizontal wiring on the lower circuit structure, and a middle circuit structure on the middle wiring structure and including a stacked structure of alternating wiring and insulation layers. A channel structure extends through the stacked structure and contacts the horizontal wiring. A contact plug contacting the first lower conductive pattern and the horizontal wiring is in the middle wiring structure. A lowermost end of the channel structure is farther from a top of the substrate than a bottom of the horizontal wiring. An uppermost end of the contact plug is farther from the top of the substrate than the bottom of the horizontal wiring. The uppermost end of the contact plug is closer to the top of the substrate than a lowermost end of the wiring layers.

Disclosed are a three-dimensional flash memory aimed at integration, and a method for manufacturing same. According to an embodiment, a three-dimensional flash memory comprises: multiple memory cell strings formed on a substrate so as to extend in a direction, each of the multiple memory cell strings comprising a channel layer and an electric charge storage layer surrounding the channel layer; multiple word lines connected perpendicularly to the multiple memory cell strings; and at least one intermediate wire layer formed at an intermediate point with regard to the direction in which the multiple memory cell strings are formed to extend, the at least one intermediate wire layer being selectively available as a source electrode or as a drain electrode with regard to each of the multiple memory cell strings. At least one of the multiple memory cell strings is formed in a free area secured among the multiple word lines as a result of inclusion of the at least one intermediate wire layer in the three-dimensional flash memory.

Methods for fabricating a semiconductor structure are disclosed. According to some aspects, a first layer is formed on a substrate, and an etch operation is performed to form an opening extending vertically through the first layer. A thermal treatment is performed on the substrate to remove a residual that residues in the opening when forming the opening. At least an oxygen gas is provided in the thermal treatment to react with the residual at a treatment temperature between 800° C. and 1,300° C.

Methods for forming a semiconductor device are disclosed. According to some aspects, a first implantation is performed on a first of a first semiconductor structure to form a buried stop layer in the first substrate. A second semiconductor device is formed. The first semiconductor structure and the second semiconductor device are bonded. The first substrate is thinned and the buried stop layer is removed, and an interconnect layer is formed above the thinned first substrate.