A semiconductor memory device includes a substrate, a plurality of first conductive layers and a plurality of first insulating layers alternately arranged in a first direction intersecting the substrate, a first semiconductor layer extending in the first direction and facing the first semiconductor layers and the first insulating layers, a first charge storage layer disposed between the first conductive layers and the first semiconductor layer, and a second semiconductor layer connected to one end of the first semiconductor layer in the first direction. The first insulating layers at least partially contains a first element. The first element is at least one of phosphorus (P), arsenic (As), carbon (C), and argon (Ar).

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

A semiconductor device and a data storage system, the device including a lower structure; and an upper structure on the lower structure and including a memory cell array, wherein the lower structure includes a semiconductor substrate, first and second active regions spaced apart from each other in a first direction on the semiconductor substrate, the first and second active regions being defined by an isolation insulating layer on the semiconductor substrate, and first and second gate pattern structures extending in the first direction to cross the first and second active regions, respectively, on the semiconductor substrate, the first gate pattern structure and the second gate pattern structure have first and second end portions spaced apart from each other in a facing manner in the first direction, respectively, and the first and second end portions are concavely curved in opposite directions away from each other in a plan view.

Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

A highly reliable memory device is provided. In a method for manufacturing a memory device that includes a first insulator, a first conductor including a first opening over the first insulator, a second insulator including a second opening over the first conductor, a second conductor including a third opening over the second insulator, a third insulator over the second conductor, and a semiconductor provided in the first opening to the third opening, the first insulator is formed, the first conductor is formed over the first insulator, the second insulator is formed over the first conductor, a fourth insulator is formed over the second insulator, the third insulator is formed over the fourth insulator, the third opening is formed in the fourth insulator, the second opening is formed in the second insulator, the first opening is formed in the first conductor, the semiconductor is formed in the first opening to the third opening, the fourth insulator is removed, and the second conductor is formed between the second insulator and the third insulator.

A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a conductive gate contact penetrating a contact region of a stepped stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked.

A semiconductor device includes a stack structure, first separation patterns passing through the stack structure, a second separation pattern passing through at least a portion of the stack structure between the first separation patterns, and a cutting channel structure passing through the stack structure and having an end portion partially cut by the second separation pattern. A channel layer of the cutting channel structure has a ring shape cut by the second separation pattern to have end portions of the channel layer which are spaced apart from each other.