A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and first alignment marks; forming memory control circuits including first single crystal transistors, where the first single crystal transistors include portions of the single crystal layer; forming at least one second level above the first level; performing a first etch step including etching lithography windows within the at least one second level; performing a first lithographic step over the at least one second level aligned to the first alignment marks; and performing additional processing steps to form a plurality of first memory cells within the at last one second level, where each of the plurality of first memory cells include one of a plurality of second transistors, and where the plurality of second transistors are aligned to the first alignment marks with a less than 40 nm alignment error.

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer disposed above the plurality of first transistors; a second metal layer disposed above the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed above the plurality of fourth transistors; a fourth metal layer disposed above the third metal layer; and a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where the device includes an array of memory cells, and where at least one of the memory cells includes one of the plurality of third transistors.

A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

A semiconductor device includes: conductive layers and interlayer insulating layers, which are alternately stacked; a select conductor spaced apart from the conductive layers; cell plugs penetrating the conductive layers, the interlayer insulating layers, and the select conductor; and an auxiliary conductor in contact with the select conductor.

Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least two metal layers; a plurality of logic gates including the at least two metal layers interconnecting the plurality of first transistors; a plurality of second transistors disposed atop the at least two metal layers; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least two rows by two columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, and where at least one of the second transistors include a metal gate.