A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

A semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.

A semiconductor memory device includes first conducting layers and a first semiconductor layer opposed to the first conducting layers. If a concentration of the dopant in the first semiconductor layer is measured along an imaginary straight line, the concentration of the dopant has: a maximum value at a first point, a minimum value in a region closer to the first conducting layer than the first point at a second point; and a minimum value in a region farther from the first conducting layer than the first point at a third point. The second point is nearer to an end portion of the first semiconductor layer on the first conducting layer side than that on the opposite side. The third point is farther from the end portion on the first conducting layer side than that on the opposite side.

A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.

A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a stacked body including alternately stacked interlayer insulating layers and conductive patterns, and channel structures penetrating the stacked body. Each of the channel structures may include a channel layer vertically extending up to the height of the upper portion of at least one upper conductive pattern disposed uppermost, among the conductive patterns, a memory layer surrounding the channel layer and extending from the lower interlayer insulating layer to the height of the middle portion of the upper conductive pattern, and a doped semiconductor pattern disposed above the channel layer and the memory layer.

The present application provides a three-dimensional memory and a fabrication method for the same. The method includes forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure, forming a selection stack structure stacked on the storage stack structure and forming a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. The width of the selection channel structure is smaller than the width of the storage channel structure on a plane parallel to the substrate and forming a TSG cut structure that penetrates the selection stack structure. The three-dimensional memory and the fabrication method for the same increases the process window for the TSG cut structure formed between the selection channel structures and improves the storage density.

A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, a channel structure, and a semiconductor structure. The stack structure includes a plurality of word lines and a select gate line formed on the doped semiconductor layer. The channel structure extends through the plurality of word lines along a first direction and in contact with the doped semiconductor layer. The semiconductor structure extends through the select gate line along the first direction and in contact with the channel structure. The select gate line extends along a second direction perpendicular to the first direction, and the drain select gate line around the semiconductor structure is insulated from the drain select gate line around an adjacent semiconductor structure. A width of the semiconductor structure is less than a width of the channel structure.

A semiconductor storage device includes a stack, a columnar body, and a second conductive layer. The stack includes a plurality of first conductive layers and a plurality of insulating layers. In the stack, the plurality of first conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The second conductive layer is connected to the columnar body. The columnar body includes an insulating core, a memory film, and a semiconductor channel. The memory film is provided between the plurality of first conductive layers and the insulating core. The semiconductor channel is provided between the insulating core and the memory film. An upper surface of the insulating core is located lower than an upper end of the columnar body. The second conductive layer has a main body portion and a protrusion. The protrusion protrudes from the main body portion toward the upper surface of the insulating core, and extends in the first direction within the columnar body. The protrusion is in contact with the semiconductor channel on a bottom surface or a side surface of the protrusion.