A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors.

A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

A medical observation apparatus including: an arm including a plurality of links connected to each other via a joint, the arm having at least three or more degrees of freedom implemented by a rotation operation about a rotation axis; an imaging device supported by the arm; and an arm controller that controls an operation of the arm. When a posture of the arm is in a predetermined state, and when a predetermined input for moving the arm about a rotation axis orthogonal to a second axis that is a second rotation axis from a side of the arm on which the imaging device is supported and a third axis that is a third rotation axis from the side of the arm on which the imaging device is supported is detected, the arm controller makes one of the links corresponding to the third axis rotate about the third axis.

In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.

Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.