A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor. Each display pixel may also have control transistors for compensating and programming operations. The array of display pixels may have rows and columns. Row lines may be used to apply row control signals to rows of the display pixels. Column lines (data lines) may be used to apply display data and other signals to respective columns of display pixels. A bottom conductive shielding structure may be formed below each drive transistor. The bottom conductive shielding structure may serve to shield the drive transistor from any electric field generated from the adjacent row and column lines. The bottom conductive shielding structure may be electrically floating or coupled to a power supply line.

An organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) on the substrate; a pixel-defining layer (PDL) disposed on the TFT and comprising a first area having a first thickness and a second area having a second thickness greater than the first thickness, and a via hole in the first area; a pixel electrode disposed on at least a portion of the first area, and electrically connected to the TFT via the via hole; an intermediate layer on the pixel electrode, the intermediate layer comprising an emission layer (EML); and an opposite electrode on the intermediate layer. According to a method of manufacturing the organic light emitting display apparatus, the PDL is formed on the substrate and then the pixel electrode is formed on the first area.

Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.

An area of a region arranged on one side out of a display region in a direction in which scanning signal lines extend is reduced. A display apparatus includes: a partial circuit; a plurality of scanning signal lines; and a plurality of scanning signal connection wirings for connecting the partial circuit and each of the plurality of scanning signal lines. Each of the plurality of scanning signal lines extends in an X-axis direction, and is arranged with a pitch in a Y-axis direction. A plurality of ends respectively included in the plurality of scanning signal connection wirings are connected to the partial circuit, and are arranged in the Y-axis direction. A distance in the Y-axis direction between the respective centers of the two ends adjacent to each other is narrower than the pitch.

A display apparatus includes: a substrate; a first semiconductor layer on the substrate, and including a silicon semiconductor; a second semiconductor layer on the first semiconductor layer, and including an oxide semiconductor; a first conductive layer on the second semiconductor layer; at least one metal layer between the first semiconductor layer and the first conductive layer; and a first contact hole to electrically connect the first semiconductor layer to the first conductive layer. An inner surface of the first contact hole includes a side surface of the at least one metal layer.

The display apparatus includes a substrate, a first active layer disposed on the substrate, a first gate layer disposed on a layer covering the first active layer, the first gate layer including a first gate electrode, a second gate layer disposed on a layer covering the first gate layer, the second gate layer including an initialization line including a first part of a second electrode; a second active layer disposed on a layer covering the second gate layer, the second active layer including a second active region overlapping the first part of the second electrode; a third gate layer disposed on a layer covering the second active layer, the third gate layer including a second part of the second electrode overlapping the second active region; and a first source/drain layer disposed on a layer covering the third gate layer, the first source/drain layer including a first connection line.

Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.

The invention provides a preparation method of a low temperature poly-silicon thin film, a preparation method of a low temperature poly-silicon thin film transistor, and a laser crystallization apparatus, and belongs to the technical field of display. The preparation method of a low temperature poly-silicon thin film of the invention comprises: forming an amorphous silicon thin film on a transparent substrate; and performing laser annealing on said amorphous silicon thin film from a side of said amorphous silicon thin film departing from said substrate, and performing laser irradiation from a side of said substrate departing from said amorphous silicon thin film, to form a low temperature poly-silicon thin film. The preparation method of a low temperature poly-silicon thin film of the invention may not only perform laser annealing on an amorphous silicon thin film form a side of the amorphous silicon thin film departing from the substrate, but also perform laser irradiation from a side of the substrate departing from the amorphous silicon thin film, and the temperature of the amorphous silicon thin film can be retained by performing laser irradiation from a side of the substrate departing from the amorphous silicon thin film. In this way, the crystallization period of poly-silicon may be elongated, and it is possible to obtain crystal grains with larger sizes, to increase carrier mobility, and to reduce drain current.

The present invention provides an array substrate and a manufacturing method thereof. Etching stop patterns or auxiliary conductive patterns of a patterned auxiliary conductive layer are disposed corresponding to heavily doped regions of a patterned semiconductor layer, and source/drain electrodes may be electrically connected to the heavily doped regions via the etching stop patterns or the auxiliary conductive patterns. The production yield and the uniformity of electrical properties may be enhanced accordingly.

According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.