A photodiode structure is based on the use of a double junction sensitive to different wavelength bands based on a magnitude of a reverse bias applied to the photodiode. The monolithic integration of a sensor with double functionality in a single chip allows realization of a low cost ultra-compact sensing element in a single packaging useful in many applications which require simultaneous or spatially synchronized detection of optical photons in different spectral regions.

The disclosure relates to solar cell, and especially to a method for manufacturing a crystalline silicon solar cell module. The method includes: a) providing a solar cell module to be laminated, including a back plate, a first bonding layer, a crystalline silicon solar cell component, a second bonding layer and a top plate in contact in sequence, where the crystalline silicon solar cell component is a crystalline silicon solar cell or a cell string formed by connecting multiple crystalline silicon solar cells; b) laminating the solar cell module to be laminated under current injection, to obtain a laminated solar cell module; and c) installing a frame and a junction box on the laminated solar cell module, to obtain a crystalline silicon solar cell module. The crystalline silicon solar cell module is under the current injection during the laminating process, improving the performance against light-induced degradation.

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

The invention relates to a passivated emitter rear solar cell, comprising a silicon substrate having a front and back surface, a rear passivation layer on the back surface of the silicon substrate having a plurality of open holes formed therein, an aluminum back contact layer formed in the open holes of the rear passivation layer, and at least one backside soldering tab on the back surface of the silicon substrate. The backside soldering tab is formed from an electroconductive paste composition comprising conductive metallic particles, at least one lead-free glass frit, and an organic vehicle comprising at least one silicone oil.

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

An avalanche photodiode includes a GeOI substrate; an IGe absorption layer configured to absorb an optical signal and generate a photo-generated carrier; a first p-type SiGe layer, a second p-type SiGe layer, a first SiGe layer, and a second SiGe layer, where a Si content in any one of the SiGe layers is less than or equal to 20%; a first SiO.sub.2 oxidation layer and a second SiO.sub.2 oxidation layer; a first taper type silicon Si waveguide layer and a second taper type silicon Si waveguide layer; a heavily-doped n-type silicon Si multiplication layer; and anode electrodes and a cathode electrode.

After forming an absorber layer containing cracks over a back contact layer, a passivation layer is formed over a top surface of the absorber layer and interior surfaces of the cracks. The passivation layer is deposited in a manner such that that the cracks in the absorber layer are fully passivated by the passivation layer. An emitter layer is then formed over the passivation layer to pinch off upper portions of the cracks, leaving voids in lower portions of the cracks.

A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Fabrication methods for forming self aligned contacts for back contact solar cells are provided.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as holes, effectively increase the absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. Their thickness dimensions allow them to be conveniently integrated on the same Si chip with CMOS, BiCMOS, and other electronics, with resulting packaging benefits and reduced capacitance and thus higher speeds.