A method comprises providing a semiconductor body with a top side. A mask is applied on the top side of the semiconductor body, wherein the mask comprises at least one first section and at least one second section. The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. A channel region of a first conductivity type is formed in the semiconductor body in the area of the at least one first section. Forming the channel region comprises implanting first-type dopants through the top side into the semiconductor body. An auxiliary layer is deposited on a lateral side of the at least one second section, the lateral side facing towards the at least one first section.

A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO.sub.2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

The present disclosure provides a process for manufacturing a vertically conducting power devices. An example includes: in a body, containing semiconductor material and having a first electrical conductivity, forming body regions, having a second electrical conductivity opposite the first electrical conductivity; forming, in respective body regions, source regions, having the first electrical conductivity; forming gate structures each comprising an insulating gate region, a conductive gate region on the insulating gate region, and a passivation gate region on the conductive gate region, wherein the conductive gate region partially overlaps the source regions of respective adjacent body regions; and forming a source metallization region on the body and gate structures comprising contact portions with respective source regions between adjacent gate structures. Forming contact portions includes: forming a spacer dielectric layer on the gate structures and the body; and etching the spacer dielectric layer anisotropically up to the source regions.

The invention provides a transistor. The transistor includes a well region arranged in a substrate, a gate structure arranged on the well region, a gate oxide layer, wherein a first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer, a first doped region and a second doped region arranged in the well region, wherein along the horizontal direction, the distance between the first doped region and the first portion of the gate oxide layer is greater than the distance between the second doped region and the second portion of the gate oxide layer, and a salicide block located on the substrate and at one side of the gate structure, wherein the salicide block is located between the first portion of the gate oxide layer and the first doped region.

A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.