A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

A semiconductor structure includes a gate structure on a substrate and a spacer on the substrate and covering sidewalls of the gate structure. The gate structure includes an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer, and a metal portion on the high-k dielectric layer. The spacer covers sidewalls of the interfacial layer, the high-k dielectric layer, and the metal portion of the gate structure. A bottom width of a portion of the spacer on the sidewall of the interfacial layer is 1.1 times of a middle width of another portion of the spacer on the sidewall of the metal portion.

A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH.sub.4)(NO.sub.3)),(CAN).

A method of manufacturing a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a dummy gate structure formed thereon and an offset spacer formed on a sidewall of the dummy gate structure. The method further includes removing the dummy gate structure to form a gate trench, forming a high-k dielectric layer on the bottom and the sidewall of the gate trench, and forming a cover layer over the high-k dielectric layer. The cover layer has a thickness that is greater at the corners of the bottom of the gate trench than in the middle region of the bottom of the gate trench.

To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.