A method of fabricating a semiconductor device is disclosed. A semiconductor substrate is provided. A high-voltage well and a pre-recessed region are formed in the semiconductor substrate. A drift region is formed in the high-voltage well. A recessed channel region is formed adjacent to the drift region. A heavily doped drain region is formed in the drift region and spaced apart from the recessed channel region. An isolation structure is formed between the recessed channel region and the heavily doped drain region in the drift region. The isolation structure overlaps with the pre-recessed region. A buried gate dielectric layer is formed on the recessed channel region. A top surface of the buried gate dielectric layer is lower than a top surface of the heavily doped drain region. A gate is formed on the buried gate dielectric layer.

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

The present invention provides an image pickup device that recognizes the object that the user is attempting to capture as the subject, tracks the movement of that subject, and can continue tracking the movement of the subject even when the subject leaves the capturing area so that the subject can always be reliably brought into focus. The image pickup device includes a main camera that captures the subject; an EVF that displays the captured image captured by the main camera, a sub-camera that captures the subject using a wider capturing region than the main camera, and a processing unit that extracts the subject from the captured images captured by the main camera and the sub-camera, tracks the extracted subject, and brings the subject into focus when an image of the subject is actually captured. When the subject moves outside of a capturing region of the main camera, the processing unit tracks the subject extracted from the captured image captured by the sub-camera.

The present description concerns a transistor comprising a channel region extending in a first direction between a drain region and a source region of a semiconductor layer and a gate structure topping the channel-forming region and comprising a gate insulator topped with a gate region; the channel-forming region comprising a first epitaxial channel region having a first length in the first direction, and a second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and the gate insulator comprising first portions having a first thickness on either side of the first channel region, and a second portion of a second thickness on the first channel region, the second thickness being smaller than the first thickn

In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

A semiconductor device includes a substrate having an active region, a recessed region in the active region, a gate dielectric layer on the substrate in the recessed region, a gate structure on the gate dielectric layer, and a doped region in the active region at two sides of the recessed region, wherein a depth of the recessed region is smaller than a depth of the doped region.

An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.

A method includes etching a trench in a substrate adjacent to a gate structure, wherein the trench includes a bottom surface and a tip portion extending under a spacer of the gate structure. The method further includes epitaxially growing a first semiconductor material in the trench, wherein the first semiconductor material covers an entirety of the bottom surface of the trench, and the first semiconductor material grows in the tip portion. The method further includes epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material, the second semiconductor material covers the first semiconductor material, and the second semiconductor material directly contacts the substrate between the bottom surface of the trench and the tip portion.

A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure in a silicon recess on the silicon portion of the hybrid device. The silicon recess contains a silicon recess nitride sidewall. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate dielectric layer disposed within the substrate in a first region of the substrate; a first gate electrode disposed within the substrate and at least laterally surrounded by the gate dielectric layer; a plurality of first protection structures over the first gate electrode; a second protection structure over the first gate electrode and laterally surrounding first protection structures from a top-view perspective; and a second gate electrode disposed over the substrate in a second region of the substrate. The plurality of first protection structures and the second protection structure have upper surfaces level with an upper surface of the second gate electrode.