Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

A semiconductor device includes a substrate, first and second metals, and a second semiconductor material. The substrate includes a first semiconductor material and has first and second substrate portions. The first metal is reacted with the first substrate portion of the substrate. The second semiconductor material is above the second substrate portion of the substrate and is different from the first semiconductor material. The second metal is reacted with the second semiconductor material.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first horizontal axis that is parallel to a substrate; a P layer comprising a PMOS device having a P channel, source, and drain that are all intersected by a second horizontal axis that is parallel to the substrate; a first gate, corresponding to the N channel, which intersects the second horizontal axis; and a second gate, corresponding to the P channel, which intersects the first horizontal axis. Other embodiments are described herein.

A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical dimension to meet the target fin critical dimension.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.

To provide a mixer and a semiconductor device which each have a small circuit area and each of which operation capability is inhibited from being decreased due to heat. The mixer includes a differential portion, a current source, a first load, an input terminal, and a first output terminal; the differential portion includes a first and a second transistor; and each of the first and the second transistors includes a metal oxide in a channel formation region. A first terminal of each of the first and the second transistors is electrically connected to the input terminal and a current source and a second terminal of the first transistor is electrically connected to a first terminal of the first load and the first output terminal. The first load has a function of supplying a current between the first terminal and a second terminal of the first load by application of voltage to the second terminal of the first load, and the current source has a function of supplying a constant current to the current source from the first terminal of each of the first and the second transistors. The current source includes a transistor including silicon in a channel formation region, and the differential portion is positioned above the current source.

Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.