FORMATION OF OHMIC CONTACTS FOR A DEVICE PROVIDED WITH A REGION MADE OF III-V MATERIAL AND A REGION MADE OF ANOTHER SEMICONDUCTOR MATERIAL

Abstract

A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.

Claims

1. A Method of producing contact zones for a transistor device including the following steps: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones based on a semiconductor and metal compound and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while carrying out an N-doping of the III-V material or by increasing the N-doping of the III-V material.

2. The method according to claim 1, wherein said other material is Si, or Ge, or SiGe, the semiconductor of the compound being chosen from Si, Ge, or SiGe so as to constitute an N-type dopant of the III-V material.

3. The method according to claim 1, wherein the compound is formed by sputtering.

4. The method according to claim 3, wherein the compound is formed by the sputtering of a first target based on the semiconductor material and of a second target based on the metal material, the first target and the second target being arranged in a same deposition enclosure or in a same deposition equipment.

5. The method according to claim 3, wherein the compound is formed by sputtering of a target based on a semiconductor material and a metal material.

6. The method according to claim 1, wherein, prior to the deposition of the layer of said compound at step a) a semiconductor layer is deposited on the first semiconductor regions and on the second semiconductor regions, the layer based on the compound being deposited on this semiconductor layer, the semiconductor layer being based on an N-type dopant of the III-V material, in particular the same semiconductor as the semiconductor of the compound.

7. The method according to claim 6, wherein the compound and the semiconductor layer are formed in a same deposition enclosure or in a same deposition equipment.

8. The method according to claim 6, wherein prior to the formation of the semiconductor layer a step of cleaning is carried out.

9. The method according to claim 1, wherein the first semiconductor regions are source and drain regions of the first transistor exposed by a first cavity, the second semiconductor regions are source and drain regions of the second transistor exposed by a second cavity, the first cavity and the second cavity being formed beforehand at step a) in a masking layer produced on the substrate and covering the transistors.

10. The method according to claim 9, wherein prior to the formation of the first cavity and the second cavity, a first protection zone is produced on a gate of the first transistor and a second protection zone is produced on a gate of the second transistor.

11. The method according to claim 10, wherein the first protection zone and the second protection zone are produced by: formation in the masking layer of openings exposing respectively a gate of the first transistor and a gate of the second transistor, removal of a portion of the gate of the first and the gate of the second transistor, so as to form holes in the extension of the openings, deposition of a protective material in the holes.

12. The method according to claim 10, further including after step a), the filling of the first cavity and/or the second cavity using at least one metal, so as to form pads.

13. The method according to claim 12, wherein the thermal annealing carried out at step b) is carried out after this filling.

14. The method according to claim 1, wherein the second semiconductor regions and the compound are based on the same semiconductor.

15. The method according to claim 14, wherein: the second semiconductor regions are based on germanium, the compound being based on germanium and preferentially TiGe.sub.2, or CoGe.sub.2 or NiGe, or the second semiconductor regions are based on silicon, the compound being based on silicon and preferentially TiSi.sub.2, or NiSi, or CoSi.sub.2.

16. A Transistor device including: a first N-type transistor provided with first semiconductor source and drain region(s) based on a III-V material, a second P-type transistor provided with second semiconductor source and drain region(s) based on a material different from the III-V material, first contact zones based on a semiconductor and metal compound being formed on the first source and drain regions, second contact zones based on the compound being formed on the second source and drain regions, the semiconductor of the compound being an N-type dopant of the III-V material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention will be better understood on reading the description of examples of embodiment given for purely indicative purposes and in no way limiting, while referring to the appending drawings in which:

[0049] FIGS. 1A-1L serve to illustrate an example of method for producing contact zones on semiconductor regions of different nature and resting on a same substrate;

[0050] FIGS. 2A-2B illustrate a variant of embodiment of the first example of method.

[0051] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to make it easier to go from one figure to the next.

[0052] The different parts represented in the figures are not necessarily according to a uniform scale, in order to make the figures more legible.

[0053] Furthermore, in the description hereafter, terms that depend on the orientation of the structure such as upper, superficial, lateral apply in considering that the structure is oriented in the manner illustrated in the figures.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0054] An example of method for producing contact zones based on a metallic semiconductor and metal compound for transistors of different types will now be given in relation with FIGS. 1A-1L.

[0055] Reference is firstly made to FIG. 1A in which a first transistor T.sub.1, and a second transistor T.sub.2 are represented during fabrication.

[0056] The transistors T.sub.1, T.sub.2 are arranged on a same substrate, which may be of semiconductor on insulator type. Semiconductor on insulator substrate is taken to mean a substrate formed of a support layer 1 which may be semiconductor and is coated with an insulator layer 2, for example a buried silicon oxide, covering the support layer 1, itself coated with at least one superficial semiconductor layer 3.

[0057] The superficial semiconductor layer 3 includes a first semiconductor zone 3a based on a first semiconductor material 4 and a second semiconductor zone 3b based on a second semiconductor material 6, the first and second zones 3a, 3b being arranged on and in contact with the insulating layer 2.

[0058] The first semiconductor material 4 is a III-V material for example based on InGaAs, or based on InAs, or InGaSb or GaSb.

[0059] The second semiconductor material 6 is preferably a material favorable to the conduction by holes and may be based on Ge or Si or SiGe, for example p-Ge or p-Si or p-(SiGe). Thus, the first transistor T.sub.1 may be an N-type transistor, in particular NMOS, whereas the second transistor T.sub.2 may be a P-type transistor, in particular PMOS.

[0060] The first transistor T.sub.1 comprises semiconductor source 12 and drain 13 regions which may be in the form respectively of N+ doped regions formed in the first semiconductor material 4, whereas the second transistor T.sub.2 is provided with semiconductor source and drain regions 22 and 23 which can be P+ doped and formed in the second semiconductor material 6.

[0061] The transistors T.sub.1, T.sub.2 each comprise a channel region 10 respectively in the first semiconductor material 4 and in the second semiconductor material 6, each channel region 10 being surmounted by a gate dielectric zone 17 and a gate 18, 28. Isolating spacers 19 may be provided against the lateral faces of the gates, whereas isolating zones 21 of STI (shallow trench isolation) type may also be formed between the transistors T.sub.1 and T.sub.2, in order to electrically isolate the latter from each other.

[0062] FIG. 1A illustrates a step of producing a masking layer 30 deposited on the substrate and covering the transistors T.sub.1 and T.sub.2. This masking layer 30 may be isolating and for example based on a silicon oxide.

[0063] Then, protection zones 35, 36 are formed on the gates of the transistors T.sub.1 and T.sub.2. To do so, it is firstly possible to produce openings 32, 33 in the masking layer 30 exposing respectively the gate of the first transistor T.sub.1 and the gate of the second transistor T.sub.2.

[0064] Advantageously, a portion of the gates 18, 28 is then removed at the level of their upper face. This removal may be carried out by selective etching of the gate material. The selective etching may be carried out for example using an etching plasma based on HBr when the gate material is for example polysilicon (FIG. 1B).

[0065] The protection zones 35, 36 may then be produced by deposition of a layer 34, for example based on dielectric material, in the openings 32, 33 (FIG. 1C).

[0066] When the layer 34 is deposited over the entire wafer, a removal of portions of the layer 34 that extend beyond the mouth of the openings 32, 33 is then carried out. Such a removal may be carried out for example by CMP (chemical mechanical planarization) such that at the end of the planarization, the upper face of the protection zones 35, 36 and the upper face of the layer 34 of dielectric material are at the same level (FIG. 1D).

[0067] Cavities are then produced in the masking layer 30, in order to expose at least one part of the source and drain regions on either side of the transistor gates.

[0068] To do so, a mask 41 may firstly be formed for example made of photosensitive resin in which holes 42, 43 are made opposite respectively the first transistor T.sub.1 and the second transistor T.sub.2 (FIG. 1E).

[0069] These holes 42, 43 are then extended to form cavities 47, 48 in the masking layer 30 in order to create emplacements for source and drain contacts (FIG. 1F).

[0070] The mask 41 of photosensitive resin (FIG. 1G) is then removed.

[0071] A structure is thereby produced in which, with the exception of the source and drain regions 12, 13 of the first transistor and 22, 23 of the second transistor exposed respectively by the first cavity 47 and the second cavity 48, the remainder of the upper face of the substrate is covered by the masking layer 30, the respective gates 18, 28 of the transistors being covered by the protection zones 35, 36.

[0072] A cleaning of the source and drain regions may then be carried out for example using a plasma or a wet method or a combination of the two in order notably to avoid conserving an oxide at the surface of these regions.

[0073] A deposition of a semiconductor layer 52 is then carried out on the respective parts of the source and drain regions of the first and the second transistor that are exposed by the cavities 47, 48 (FIG. 1H). The semiconductor layer 52 is based on a semiconductor capable of constituting an N-type dopant of the III-V material of regions.

[0074] Preferably, the semiconductor layer 52 is based on a semiconductor that is not likely to modify the doping of the source and drain regions of the P-type transistor or at least alter the electrical properties of the source and drain regions of the P-type transistor.

[0075] The semiconductor layer 52 may for example be based on germanium.

[0076] Thus, the semiconductor of the layer 52 may be identical to the second semiconductor material 6 in which the channel region of the second transistor is provided. The semiconductor layer 52 may thus be provided to dope the III-V material without this impacting the semiconductor regions 22, 23 based on the second semiconductor material 6.

[0077] The thickness of the semiconductor layer 52 may be of the order of several nanometers, for example comprised between 1 and 10 nm and advantageously between 2 and 5 nm.

[0078] The semiconductor material of the semiconductor layer 52 may be deposited in amorphous form, for example by CVD (chemical vapor deposition) or by PVD (physical vapor deposition), ALD (atomic layer deposition), or by electrochemical or electroless wet deposition. The deposition may be plasma enhanced.

[0079] Advantageously, the semiconductor layer 52 is produced by a sputtering method in which for example a germanium target is used. With such a method, it is possible to do without an epitaxy step.

[0080] Prior to the deposition of the semiconductor layer 52, a step of surface preparation of the exposed parts of the source and drain regions may be carried out. The surface preparation may be carried for example using a dilute HCl or dilute HF/HCl solution.

[0081] This surface preparation may advantageously be carried out in situ, that is to say in the same deposition machine, in particular in a same enclosure as that used to form the semiconductor material 52. In this case, such a cleaning may also be carried out for example using a direct or remote plasma based on Ar, or He, or NH.sub.3, or H.sub.2 or a mixture of some of these gases.

[0082] A deposition of a layer based on a metallic compound 54 based on metal and semiconductor on the semiconductor layer 52 (FIG. 11) is then carried out.

[0083] This compound 54 includes a semiconductor capable of constituting an N-type dopant of the III-V material of the semiconductor regions 12 and 13. The semiconductor based on which the compound is formed may be chosen so as not to modify the doping of the source and drain regions of the P-type transistor.

[0084] The compound 54 is thus also chosen as a function of the band structure of the second semiconductor material 6 preferably so as to be mid-gap compared to the second semiconductor 6, that it to say of which the Fermi level coincides with the middle of the forbidden band of the semiconductor material 6.

[0085] In the case, for example, where the first semiconductor material 4 of III-V type is InGaAs and where the second semiconductor material 6 is Ge, it is possible to choose the compound 54 for example from the following compounds: TiSi.sub.2, TaSi.sub.2, WSi.sub.2 CoSi.sub.2, NiSi.sub.2, NiSi, Ni.sub.2Si, CoSi.sub.2, Ti(SiGe).sub.2 of structure C49, Ni(SiGe) of structure B31, Ta(SiGe).sub.2 of structure C40.

[0086] Advantageously, the semiconductor of this compound 54 is the same as that based on which the semiconductor layer 52 is formed, for example germanium when the source 22 and drain 23 regions of the second transistor T.sub.2 are based on germanium.

[0087] Thus, in the aforementioned case where the regions 12, 13 are made of InGaAs and where the regions 22, 23 are made of Ge, the compound 54 may be chosen for example from: TaGe.sub.2, WGe.sub.2, TaGe.sub.2, or preferably from the following compounds: NiGe, TiGe.sub.2, CoGe.sub.2. Such compounds have the advantage of making it possible to produce contact zones of lower resistivity. They are also easier to elaborate.

[0088] The layer of the compound 54 produced may have a thickness comprised for example between 2 and 25 nm and preferentially comprised between 5 nm and 15 nm.

[0089] The compound 54 may be deposited for example by CVD (chemical vapor deposition) or PVD (physical vapor deposition) or ALD (atomic layer deposition), by an electrochemical or electroless method. The deposition may potentially be plasma enhanced.

[0090] Advantageously, the compound layer 54 is produced by a sputtering method in which one or more targets are used from which is or are extracted the element or the elements to deposit. The compound 54 is here obtained directly by deposition without a thermal annealing being necessary to obtain it.

[0091] Such a sputtering method makes it possible to control easily the respective proportions of metal and semiconductor material in the compound 54

[0092] For example, when the compound 54 is based on NiGe, it is possible to implement a compound with an atomic proportion of Ni of 50% and an atomic proportion of Ge of 50%, or produce NiGe rich in germanium that is to say with an atomic proportion of Ge comprised between 50 and 90%.

[0093] Such a sputtering method may potentially make it possible to produce a compound layer 54 comprising a gradient of concentration of semiconductor material. For example, it is possible to implement a layer of Ni.sub.yGe.sub.1-y with y varying in accordance with the depth at which it is situated in this layer.

[0094] The sputtering deposition method may be carried out using a first target based on the semiconductor material, for example a germanium target as well as a second target based on the metal material, for example a nickel target. The first target and the second target are then arranged in a same enclosure or in different deposition enclosures of a same deposition equipment. With such a sputtering method, the different constituents of the compound 54 may thus be deposited without the substrate leaving the deposition equipment in which said deposition is carried out.

[0095] In a variant, a single target based on the compound that it is wished to deposit, for example a NiGe target, is used.

[0096] Advantageously, it is possible to form the semiconductor layer 52 and the compound 54 by successive sputtering steps carried out in a same deposition equipment or even in a same deposition enclosure.

[0097] This therefore avoids removing the substrate from the deposition equipment which would lead to returning the semiconductor material of the layer 52 to the ambient air of the clean room in which is located the deposition equipment and would be likely to lead to a surface oxidation of the semiconductor layer 52.

[0098] Compared to a silicidation method in which a deposition of semiconductor would be carried out in one equipment then a deposition of metal in another equipment, it thus avoids creating an air-break, which could potentially create an oxide and require carrying out a step of cleaning prior to the deposition of metal. After the deposition of the compound 54, at least one thermal annealing is carried out.

[0099] Such an annealing makes it possible to homogenize the metal and semiconductor compound and, when it is not in crystalline form, to crystallize it.

[0100] The thermal annealing further makes it possible to carry out an over-doping of the III-V material of the semiconductor source and drain regions 12, 13 of the N-type transistor T.sub.1. Over-doping is taken to mean that the doping of already doped semiconductor regions 12, 13 is increased.

[0101] Contact zones 74 based on a semiconductor and metal compound are thus formed on the semiconductor source and drain regions 12, 13 of the first transistor T.sub.1. Contact zones 76 based on the same semiconductor and metal compound are formed concomitantly on the semiconductor source and drain regions 22, 23 of the second transistor T.sub.2. In the case where the layer 52 is made of Ge and the compound 54 is NiGe contact zones 74, 76 made of Ni.sub.yGe.sub.1-y are formed.

[0102] The thermal annealing may be a rapid annealing, i.e. of a duration that may be comprised for example between 10 and 600 s, preferentially between 30 and 120 seconds at a temperature comprised between 200 C. and 600 C., preferably between 250 C. and 400 C.

[0103] The annealing is preferably carried out under inert atmosphere.

[0104] An annealing method of type commonly called spike annealing, or of RTP (Rapid Thermal Process) type for which a high temperature ramp is implemented may be carried out. In a variant, this annealing is carried out using a laser or by microwave energy.

[0105] Thus, with such a method ohmic contacts 74, 76 are produced with a same annealing on the source and drain regions of the transistors while carrying out the over-doping of the source and drain regions of the first transistor.

[0106] In this example of embodiment, the respective gates 18, 28 of the transistors are protected by the protection zones 35, 36 so much so that the semiconductor and metal compound is not formed on the gates.

[0107] Then, a deposition of metal material 81 may be carried out so as to fill the cavities 47, 48 produced on either side of the gates of transistors T.sub.1, T.sub.2 and exposing the contact zones (FIG. 1K).

[0108] It is then possible to remove portions of metal material extending beyond the mouth of the holes. Such a removal may be carried out for example by CMP while stopping at the level of the protection zones 35, 36 arranged on the gates 18, 28 (FIG. 1L). Metal pads 82 are thereby formed on the ohmic contacts made of metal and semiconductor compound.

[0109] With such a method as described previously a selective removal is not necessary in so far as the formation of the metal and semiconductor compound is localized on portions of source and drain regions, thanks to the cavities 47, 48 formed in the masking layer 30 by a method of SAC (self-aligned contact) type.

[0110] In the example of embodiment that has been given previously, the deposition of the metallic compound 54 based on semiconductor and metal is preceded by that of the semiconductor layer 52.

[0111] According to an embodiment variant, a deposition of the compound 54 based on semiconductor and metal is carried out directly on the source and drain regions without intermediate semiconductor layer. In this case, the stoichiometry of the compound 54 and its proportion of semiconductor are adapted to be able to conserve the effect of over-doping at the moment of the thermal annealing. In the case for example where the compound 54 is based on Ni.sub.xGe.sub.1-x preferably x<0.5 is chosen.

[0112] The compound 54 and the layer 52 are adapted as a function of the composition of semiconductor source and drain regions.

[0113] In the case, for example, where the first semiconductor material 4 of III-V type is InGaAs and where the second semiconductor material 6 is Si, Ge or SiGe, the compound 54 may be chosen for example from the following compounds: Ti(SiGe).sub.2 of structure C49, Ni(SiGe) of structure B31, Ta(SiGe).sub.2 of structure C40.

[0114] When the first semiconductor material 4 of the source and drain regions of the first transistor is InGaAs and the second semiconductor material 6 of the source and drain regions of the second transistor is Si it is also possible to choose the compound 54 from the following compounds: TaGe.sub.2, WGe.sub.2, TiGe.sub.2, NiGe, CoGe.sub.2.

[0115] Advantageously, the semiconductor based on which the compound 54 is formed is the same as that of the semiconductor layer 52, for example silicon when the source 22 and drain 23 regions of the second transistor are based on silicon. Thus, in the aforementioned case where the regions 12, 13 are made of InGaAs and where the regions 22, 23 are made of Si, it is possible to choose the compound 54 for example from: TaSi.sub.2, WSi.sub.2 NiSi.sub.2, Ni.sub.2Si, or preferably from: TiSi.sub.2, CoSi.sub.2, NiSi.

[0116] A variant of one or the other of the embodiment examples described previously provides for only carrying out the thermal homogenization annealing of the compound and over-doping after having carried out the filling of the cavities 47, 48 by the metal 81 to form the metallic pads 82 on the ohmic contacts.

[0117] Thus, according to this variant, the semiconductor layer 52 is deposited on the exposed parts of the source and drain regions, the compound layer 54 is then formed on this semiconductor layer 52. Next, the metal 81 is deposited in the cavities 46, 47, which are planarized to form the metal pads 82 (FIG. 2A).

[0118] Then, the thermal annealing is carried out so as to make the compound homogenous, or even to crystallize it, in order to form contacts 74 on the source and drain regions of the first transistor T.sub.1 and contacts 76 on the source and drain regions of the second transistor T.sub.2, while carrying out an over-doping of the source and drain regions of the first transistor T.sub.1.

[0119] Another variant of embodiment of one or the other of the methods described previously provides for forming a diffusion barrier layer, for example based on TiN prior to the deposition of metal 81. Such a barrier layer may have a thickness of the order of several nanometers for example comprised between 2 and 20 nm.

[0120] A method in accordance with the invention is quite particularly adapted to the production of transistor devices produced according to advanced technology nodes and corresponding for example to gate dimensions of the order of several nanometers, in particular 7 nm.

[0121] A method in accordance with the invention is also adapted to a production of contacts based on a metal and semiconductor compound in a device dedicated to photonics.