A process for porosifying a structure including a base substrate covered with mesas, the mesas being (Al, In, Ga)N or InP mesas or (Al, In, Ga)N/(Al, In, Ga)N or InP/InP mesas, the mesas being electrochemically porosified according to the following cycle of steps: i) applying a first potential for a first duration, ii) applying a second potential for a second duration, whereby porosified mesas are obtainedincluding, from the side faces of the mesas towards the center of the mesas or vice versa, a first portion having a first porosification ratio and a second portion, the second portion having a second porosification ratio higher than the first porosification ratio or the second portion being hollowed out.

A process for porosifying a structure including a base substrate covered with mesas, the mesas being (Al, In, Ga)N or InP mesas or (Al, In, Ga)N/(Al, In, Ga)N or InP/InP mesas, the mesas being electrochemically porosified according to the following cycle of steps: i) applying a first potential for a first duration, ii) applying a second potential for a second duration, whereby porosified mesas are obtainedincluding, from the side faces of the mesas towards the center of the mesas or vice versa, a first portion having a first porosification ratio and a second portion, the second portion having a second porosification ratio higher than the first porosification ratio or the second portion being hollowed out.

A semiconductor structure includes a superlattice with two or more unit cells, wherein each of the unit cells includes a first epitaxial layer including NiO or Ga.sub.2O.sub.3. Each of the unit cells can further include a second epitaxial layer including a second epitaxial oxide material selected from Ni.sub.zGa.sub.2(1z)O.sub.32z or Ni.sub.zAl.sub.2(1z>)O.sub.32z, where 0<z<1. In some cases, the second epitaxial oxide material can include Ni.sub.x(Al,Ga).sub.yO.sub.z.

A semiconductor structure includes a superlattice with two or more unit cells, wherein each of the unit cells includes a first epitaxial layer including NiO or Ga.sub.2O.sub.3. Each of the unit cells can further include a second epitaxial layer including a second epitaxial oxide material selected from Ni.sub.zGa.sub.2(1z)O.sub.32z or Ni.sub.zAl.sub.2(1z>)O.sub.32z, where 0<z<1. In some cases, the second epitaxial oxide material can include Ni.sub.x(Al,Ga).sub.yO.sub.z.

A light emitting element includes: a first semiconductor layer including a semiconductor of a first type; a second semiconductor layer including a semiconductor of a second type different from the first type; and an active layer between the first and second semiconductor layers, the active layer including a first active area including a first well layer, and a second active area including a second well layer. The first well layer has a first band gap, and the second well layer has a second band gap smaller than the first band gap. At least a portion of the first active area is between the second active area and the second semiconductor layer. A distance between the second active area and the second semiconductor layer is equal to or greater than 0.1 times of a distance between the first and second semiconductor layers.

A light emitting element includes: a first semiconductor layer including a semiconductor of a first type; a second semiconductor layer including a semiconductor of a second type different from the first type; and an active layer between the first and second semiconductor layers, the active layer including a first active area including a first well layer, and a second active area including a second well layer. The first well layer has a first band gap, and the second well layer has a second band gap smaller than the first band gap. At least a portion of the first active area is between the second active area and the second semiconductor layer. A distance between the second active area and the second semiconductor layer is equal to or greater than 0.1 times of a distance between the first and second semiconductor layers.

A light-emitting element includes a first semiconductor layer doped to have a first polarity; a second semiconductor layer doped to have a second polarity that is different from the first polarity; an active layer placed between the first semiconductor layer and the second semiconductor layer; and an insulating layer surrounding at least the outer surface of the active layer. The insulating layer includes an insulating film surrounding the active layer, and an element dispersion agent including a magnetic metal and bonded to an outer surface of the insulating film.

A first electrode upper layer of an electrode upper layer of a display device and a second electrode upper layer are disposed to partially expose a top surface of the first electrode base layer and a top surface of the second electrode base layer, respectively. A first insulating layer of the display device includes contact portions partially exposing a top surface of the first electrode base layer, a top surface of the second electrode base layer, and a top surface of the pad electrode upper layer.

A light emitting diode (LED) comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and the p-doped portion. The light emitting region comprises: a light-emitting layer which emits light at a peak wavelength between 400 and 599 nm under electrical bias thereacross; a III-nitride layer located on the light-emitting layer; and a III-nitride barrier layer located on the III-nitride layer. The light emitting diode comprises a porous region of III-nitride material. An LED array and a method of manufacturing an LED with a peak emission wavelength between 400 nm and 599 nm under electrical bias are also provided.

A light emitting diode (LED) comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and the p-doped portion. The light emitting region comprises: a light-emitting layer which emits light at a peak wavelength between 400 and 599 nm under electrical bias thereacross; a III-nitride layer located on the light-emitting layer; and a III-nitride barrier layer located on the III-nitride layer. The light emitting diode comprises a porous region of III-nitride material. An LED array and a method of manufacturing an LED with a peak emission wavelength between 400 nm and 599 nm under electrical bias are also provided.