A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.

A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first transistor, a first insulator over the first transistor, a second transistor over the first insulator, a second insulator over the second transistor, and a capacitor over the second insulator. The first insulator has a barrier property against oxygen and hydrogen. The second transistor includes an oxide semiconductor. The second insulator includes an oxygen-excess region. The capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. The dielectric includes a third insulator having a barrier property against oxygen and hydrogen. The first insulator and the third insulator are in contact with each other on an outer edge of a region where the second transistor is located so that the second transistor and the second insulator are enclosed by the first insulator and the third insulator.

According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.

A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).

A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

An array substrate and its manufacturing method, and a display device are disclosed, and the array substrate includes a black matrix (200) disposed on a base substrate (100) and has a plurality of pixel units arranged in an array, the orthographic projection of the pattern of the black matrix (200) on the base substrate at least partially covers the gap between adjacent pixel units, and the surface of at least a portion of the black matrix (200) has a first concave-convex structure (A) capable of reflecting the light irradiated to the surface of the black matrix (200) in diffuse reflection. Because the first concave-convex structure (A) of the surface of the black matrix (200) has a diffuse reflection effect, the external light will be subjected to diffuse reflection when irradiated to the surface of the black matrix (200), thereby reducing the light intensity of the reflected light, enhancing the visibility of the area of each of the pixel units of the array substrate, and improving the display effect of picture.

A liquid crystal display panel includes a base substrate, a first step difference compensating pattern, a gate metal pattern, a semiconductor pattern, a source electrode, a drain electrode, a pixel electrode and a color filter. The first step difference compensating pattern is disposed on the base substrate and includes an inorganic material. The gate metal pattern is disposed on the first step difference compensating pattern and includes a gate electrode and a gate line electrically connected to the gate electrode. The semiconductor pattern is overlapped with the gate electrode. The source electrode is electrically connected to the semiconductor pattern. The drain electrode is electrically connected to the semiconductor pattern and is spaced apart from the source electrode. The pixel electrode is electrically connected to the drain electrode. The color filter is overlapped with the pixel electrode.

The present disclosure provides a thin-film transistor. The thin-film transistor includes a substrate including at least one trench; at least one electrode in each of the at least one trench, the at least one electrode being one or more of a gate electrode, a source electrode, and a drain electrode; and an active layer over the at least one electrode.

The present invention provides an OLED display substrate and a manufacture method thereof. The OLED display substrate comprises a substrate (10), a TFT (90) located on the substrate (10), a passivation layer (50) located on the TFT (90), a flat layer (60) located on the passivation layer (50), a connecting electrode (80) being located on the flat layer (60) and contacting the TFT (90), an anode (70) being located on the flat layer (60) and covering the connecting electrode (80), an organic emitting layer (71) located on the anode (70) and a cathode (72) located on the organic emitting layer (71); the connecting electrode (80) contacts the TFT (90) via the contact hole (81) penetrating the flat layer (60) and the passivation layer (50); the anode (70) is electrically connected to the TFT (90) via the connecting electrode (80); the short circuit between the cathode and anode of the OLED display substrate can be prevented for avoiding the current concentration and ensuring the normal illumination of the OLED.