An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

The present invention provides a TFT substrate structure and a manufacturing method thereof. In the manufacturing method of a TFT substrate structure according to present invention, a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer, wherein the modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone; portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserves the excellent electrical conduction property of graphene and thus electrical connection between the source and drain electrodes and the semiconductor layer can be achieved without formation of a via in the graphene layer, making a TFT device so manufactured showing excellent I-V (current-voltage) output characteristics and stability, saving one mask operation process, shortening the manufacturing time, and lowering down the manufacturing cost.

The present invention provides a manufacture method of a dual gate TFT substrate and a structure thereof. The manufacture method of a dual gate TFT substrate, comprises sequentially manufacturing a bottom gate (2), a first isolation layer (3), an island shaped semiconductor layer (4), a second isolation layer (5) on a substrate (1) in advance; then, deposing a second metal layer, and implementing patterning process to the second metal layer with one mask to form a source (61), a drain (62) and a top gate (63) at the same time; and then, sequentially manufacturing a third isolation layer (7) and a pixel electrode (8). It can promote the stability of the TFT for reducing the amount of the masks, and shortening the process flow, simplifying the manufacture process and diminishing the production cost. In the structure of the dual gate TFT substrate according to the present invention, the structure is simple, and the stability of the TFT is better, and easy to manufacture.

A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor comprises: a gate electrode (11), a source electrode (15) and a drain electrode (16), and the thin film transistor further comprises a buffer layer (11) which is directly provided at one side or both sides of at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16), wherein, the buffer layer (11) and at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16) directly contacting the buffer layer (11) are conformal. Therefore, the adhesion between an electrode of the thin film transistor and a film layer contacting it is improved and at the same time an atom in the electrode of the thin film transistor is effectively prevented from diffusing to the film layer connected with it, and the reliability of the thin film transistor is improved and the production cost is reduced.

The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an active layer of the TFT corresponding to a gap between a source electrode and a drain electrode includes a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer. The source electrode and the drain electrode are directly lapped onto the active layer.

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor.

The present invention provides a TFT substrate and method for manufacturing the same. The method comprises the steps of: providing a substrate; forming a TFT structure above the substrate; further forming a color resist layer above the substrate, and forming a first opening area in the color resist layer at a location corresponding to the TFT structure; forming a first black matrix in the first opening area such that the TFT structure is covered by the first black matrix; and forming a pixel electrode above the color resist layer and the first black matrix, and the pixel electrode being electrically coupled to the TFT structure through the first black matrix. By applying the method described above, the present invention is sufficient to shield the light and reduce the light transmittance effect when the panel comprising the TFT substrate is bent, such that the contrast of the panel can be improved.

A liquid crystal display device includes a TFT substrate having a display region with first and second electrodes, TFTs, scanning signal lines connected to the TFTs, a counter substrate, a liquid crystal layer sandwiched between the TFT and counter substrates, and sealed by a sealant, scanning line leads connected to the scanning signal lines and formed outside of the display region, video signal line leads connected to the video signal lines and formed outside of the display region and a shield electrode formed on the TFT substrate covering the scanning line leads but not the video signal line leads. The second electrode is connected to one of the TFTs, and liquid crystal molecules of the liquid crystal layer are driven by an electric field, which is generated between the first and second electrodes. The shield electrode is electrically connected to the first electrode and overlapped with the sealant in plan view.