The present invention provides a TFT substrate structure and a manufacturing method thereof. In the manufacturing method of a TFT substrate structure according to present invention, a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer, wherein the modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone; portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserves the excellent electrical conduction property of graphene and thus electrical connection between the source and drain electrodes and the semiconductor layer can be achieved without formation of a via in the graphene layer, making a TFT device so manufactured showing excellent I-V (current-voltage) output characteristics and stability, saving one mask operation process, shortening the manufacturing time, and lowering down the manufacturing cost.

An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.

A thin film transistor (TFT) includes a semiconductive layer, a first inter-layer drain (ILD) layer, a second ILD layer, and at least one contact hole passing through the first ILD layer and the second ILD layer. The semiconductive layer includes a channel region, a first lightly doped drain (LDD) region, a second LDD region, a first heavily doped drain (HDD) region, and a second HDD region. The at least one contact hole includes a first portion passing through the second ILD layer and a second portion passing through the first ILD layer. The second portion gradually narrows along a direction from a top to a bottom of the first ILD layer.

The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an active layer of the TFT corresponding to a gap between a source electrode and a drain electrode includes a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer. The source electrode and the drain electrode are directly lapped onto the active layer.

A method for manufacturing an array substrate, a film-etching monitoring and a film-etching monitoring device. The monitoring method comprises: monitoring and recording the transmittance reference value of a film after a film pattern is formed; and monitoring the transmittance present value of the film in real time in the process of etching an overcoating layer to form a through hole after the overcoating layer is formed on the film pattern, and monitoring the etching degree of the film by determining the variation between the transmittance present value and the transmittance reference value. The device comprises a plurality of light sources (3) and a plurality of light-sensitive probes (4) disposed in the chamber. The light sources (3) are configured to irradiate the film on a substrate; and the light-sensitive probes (4) are configured to sense the transmittance of the film.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3), a semiconductor-layer thin film (4) and a passivation-shielding-layer thin film (5) successively; forming a pattern (5) that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c) and a drain electrode (4b). The source electrode (4c) and the drain electrode (4b) are disposed on two sides of the active layer (4a) respectively and in a same layer as the active layer (4a). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.

The present disclosure relates to a new generation of laser-crystallization approaches that can crystallize Si films for large displays at drastically increased effective crystallization rates. The particular scheme presented in this aspect of the disclosure is referred to as the advanced excimer-laser annealing (AELA) method, and it can be readily configured for manufacturing large OLED TVs using various available and proven technical components. As in ELA, it is mostly a partial-/near-complete-melting-regime-based crystallization approach that can, however, eventually achieve greater than one order of magnitude increase in the effective rate of crystallization than that of the conventional ELA technique utilizing the same laser source.

The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.

A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.