The present invention provides an array substrate and a manufacturing method thereof and a liquid crystal display panel using the array substrate. The array substrate includes: a first substrate (32), a gate line formed on the first substrate (32), a data line (34) formed on the first substrate (32), a thin-film transistor array formed on the first substrate (32), a pixel electrode (36) formed on the thin-film transistor array, a first passivation layer (38) formed on the pixel electrode (36), the data line (34), and the thin-film transistor array, a black matrix (42) formed on the first passivation layer (38), and a common electrode (44) formed on the black matrix (42) and the first passivation layer (38). The present invention arranges the black matrix formed on the array substrate to reduce the parasitic capacitance between the common electrode and the gate line and the data line so as to help enhance uniformity of voltage on the common electrode.

A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate insulating layer on the gate line and the first auxiliary pattern forming a data line in the display region and a second auxiliary pattern in the non-display region over the gate insulating layer, wherein the data line crosses the gate line to define a pixel region forming a passivation layer on the data line and the second auxiliary pattern, and the passivation layer including first and second contact holes respectively exposing the first and second auxiliary patterns forming a planarization layer and a bridge pattern on the passivation layer forming a pixel electrode on the planarization layer and in the pixel region, and a connection pattern on the bridge pattern, wherein the connection pattern contacts the first and second auxiliary patterns.

The present invention discloses a thin-film transistor and a fabricating method thereof, an array substrate and a display apparatus. An active layer in the thin-film transistor comprises a first active layer and a second active layer which are stacked; wherein, an orthographic projection of the first active layer on the substrate covers orthographic projections of the source electrode, the drain electrode as well as a gap located between the source electrode and the drain electrode on the substrate, and covers an orthographic projection of the gate electrode on the substrate; the second active layer is located at the gap between the source electrode and the drain electrode, and an orthographic projection of the second active layer on the substrate is located in a region where the orthographic projection of the gate electrode on the substrate is located.

As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.

A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

A display substrate includes a first switching element electrically connected to a gate line and that extends in a first direction and electrically connected to a data line that extends in a second direction crossing the first direction, an insulation layer disposed on the first switching element, a shielding electrode disposed on the insulation layer and a pixel electrode that partially overlap the shielding electrode. The shielding electrode includes a first portion that overlaps the data line and extends in the second direction and a second portion that overlaps the gate line and extends in the first direction.

The present invention provides a thin film transistor substrate and a display device that prevent peeling. The thin film transistor substrate includes: an insulating substrate; a thin film transistor; a first inorganic insulating layer; an organic insulating layer stacked on the first inorganic insulating layer; and a second inorganic insulating layer stacked on the organic insulating layer. The organic insulating layer includes a side covered with the second inorganic insulating layer. The first inorganic insulating layer may contain silicon oxide. The organic insulating layer may contain photosensitive resin. The second inorganic insulating layer may contain silicon nitride.

An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern. A modification process including introducing at least one gas is performed on the second transparent semiconductor pattern to transfer the second transparent semiconductor pattern into a conductive transparent top electrode.