A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

Provided are a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor having improved characteristics and a method for manufacturing the same. A thin film transistor in accordance with an exemplary embodiment includes a gate electrode, an active layer containing oxide of a first metal element and disposed to be vertically spaced apart from the gate electrode, source and drain electrodes disposed to be spaced apart from each other on the active layer, and a contact layer disposed between the active layer and the source and drain electrodes.

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a channel structure on the substrate. The channel structure includes a first intermediate layer, a channel layer, and a second intermediate layer that are stacked. The channel structure includes a gate region and source and drain regions located at both ends of the gate region. A first N-type heavily doped layer is located between the substrate and the channel structure, and the second N-type heavily doped layer is located on the side of the channel structure far from the substrate. The projections of the first N-type heavily doped layer and the second N-type heavily doped layer on the channel structure are located within the gate region. A gate is located on the gate region. The gate covers the sidewalls of the first N-type heavily doped layer, the channel layer, and the second N-type heavily doped layer.

The present disclosure provides a semiconductor structure, including: a substrate; a channel structure on the substrate, a first N-type heavily doped layer and a second N-type heavily doped layer. The channel structure includes a first intermediate layer, a channel layer, and a second intermediate layer that are sequentially arranged on the substrate, where a width of a cross-section of the channel layer is smaller than a width of a cross-section of the first intermediate layer, and the second intermediate layer covers sidewalls of the channel layer and a surface of the channel layer far from the first intermediate layer. The first N-type heavily doped layer is between the substrate and the channel structure, and the second N-type heavily doped layer is on a side of the channel structure far from the substrate.

The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.