A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

The present invention discloses a conductive structure, a method of manufacturing the conductive structure, and an array substrate. The method of manufacturing the conductive structure, comprising steps of: Forming a barrier metal film and a copper metal film in this order on a substrate, wherein the copper metal film being laminated on the barrier metal film; forming a preset photoresist pattern on the copper metal film; etching the barrier metal film and the copper metal film; oxidizing an exposed sidewall of the etched barrier metal film and an exposed sidewall of the etched copper metal film, so as to generate metal oxide layers on the exposed sidewall of the etched barrier metal film and the exposed sidewall of the etched copper metal film, respectively; and stripping off the photoresist pattern by means of a photoresist stripping liquid. In the method of manufacturing the conductive structure according to embodiments of the present invention, the exposed sidewall of the conductive structure is oxidized to generate a uniform metal oxidization layer on the exposed sidewall before removing the photoresist from the conductive structure by a wet stripping process. In this way, it can effectively prevent the interfaces between the copper metal film and the barrier metal film from being separated during performing the wet stripping process.

A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

An Al wiring film having a tapered shape is obtained easily and in a stable manner. An Al wiring film has a double-layer structure including a first Al alloy layer made of Al or an Al alloy, and a second Al alloy layer laid on the first Al alloy layer and having a composition different from a composition of the first Al alloy layer by containing at least one element of Ni, Pd, and Pt. The second Al alloy layer is etched by an alkaline chemical solution used in a developing process of a photoresist, and an end portion of the second Al alloy layer recedes from an end portion of the photoresist. Thereafter, by performing wet etching using the photoresist as a mask, a cross section of the Al wiring film becomes a tapered shape.

A method includes forming a first silicide on a substrate after patterning a gate and spacer onto the substrate. A film is deposited over the substrate. A portion of the dielectric film is removed to expose the first silicide. A portion of the first silicide is removed to form a punch through region. A liner is deposited in the punch through region. A metal layer is deposited on the liner. The substrate is annealed to form a second silicide on the substrate.

The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

A thin film transistor (TFT) device is provided. The TFT device includes a first conductive layer including a gate electrode and a connection pad. The TFT device further includes a first dielectric layer covering the gate electrode, and a semiconductor layer disposed on the dielectric layer and overlapping the gate electrode. The TFT device further includes a second dielectric layer disposed on the semiconductor layer and the first dielectric layer so as to expose first and second portions of the semiconductor layer and the connection pad. The TFT device further includes a second conductive layer which includes a source electrode portion covering the first portion of the semiconductor layer; a pixel electrode portion extending to the source electrode portion; a drain electrode portion covering the second portion of the semiconductor layer; and an interconnection portion disposed on the connection pad and extending to the drain electrode portion.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3), a semiconductor-layer thin film (4) and a passivation-shielding-layer thin film (5) successively; forming a pattern (5) that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c) and a drain electrode (4b). The source electrode (4c) and the drain electrode (4b) are disposed on two sides of the active layer (4a) respectively and in a same layer as the active layer (4a). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.