One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

A method of forming a patterned metal film layer and preparation methods of a transistor and an array substrate are disclosed, in the technical field of displays. The method of forming a patterned metal film layer of the invention comprises: sequentially depositing a sacrificial layer and a photoresist layer on a substrate, and forming a patterned sacrificial layer and a patterned photoresist layer overlying on the patterned sacrificial layer by exposure, development, and etching, wherein a side wall of the patterned sacrificial layer adjacent to a patterned metal film layer to be formed forms a chamfer; depositing a metal film layer on the substrate after finishing the above step, and removing the patterned photoresist layer and the sacrificial layer to form a patterned metal film layer.

An array substrate and a manufacturing method thereof, a display panel, and a display device are provided. The array substrate includes a substrate; a source-drain metallic layer and a first passivation metallic protective layer formed in sequence on the substrate, the source-drain metallic layer including a source electrode and a drain electrode not contacted with each other; a conductive protection layer formed on the substrate on which the first passivation metallic protection layer has been formed; and a pixel electrode formed on the substrate on which the conductive protection layer has been formed, the pixel electrode contacting the conductive protection layer.

A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.

An array substrate, a display apparatus applying the same and the assembly method thereof are provided, wherein the array substrate includes a substrate having a plurality of pixels, each of the pixels at least includes a thin film transistor (TFT) device, a first electrode, a second electrode separated from the first electrode all of which are disposed on the substrate. at least one of the first electrode and the second electrode is electrically contacted to the TFT device, and either the first electrode or the second electrode has a magnetic force generator used to generate a magnetic force substantially ranging from 10 gauss to 1000 gauss.

A TN-type array substrate and a fabrication method thereof, and a display device, the fabrication method of the TN-type array substrate includes: a step of forming a first metal layer, a gate insulating layer, an active layer, a second metal layer and a transparent conductive layer on a substrate, wherein the first metal layer includes a gate electrode, the second metal layer includes a data line, the transparent conductive layer includes a pixel electrode; and wherein the forming the second metal layer and the transparent conductive layer includes: sequentially forming a transparent conductive thin film and a metal thin film on the substrate; performing one-off patterning process on the transparent conductive thin film and the metal thin film to form a thin film transistor (TFT) channel region, the transparent conductive layer and the second metal layer.

An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. A patternized third metal layer is between the bottom transparent conductive layer and the protective layer and includes a first zone and a second zone intersecting the first zone. The first zone shields the source line. A portion of the second zone overlaps a side portion of the light shield layer that is close to the source/drain electrode.

The present invention discloses a thin-film transistor and a fabricating method thereof, an array substrate and a display apparatus. An active layer in the thin-film transistor comprises a first active layer and a second active layer which are stacked; wherein, an orthographic projection of the first active layer on the substrate covers orthographic projections of the source electrode, the drain electrode as well as a gap located between the source electrode and the drain electrode on the substrate, and covers an orthographic projection of the gate electrode on the substrate; the second active layer is located at the gap between the source electrode and the drain electrode, and an orthographic projection of the second active layer on the substrate is located in a region where the orthographic projection of the gate electrode on the substrate is located.

As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.

A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.