An array substrate and a manufacturing method thereof, a display panel, and a display device are provided. The array substrate includes a substrate; a source-drain metallic layer and a first passivation metallic protective layer formed in sequence on the substrate, the source-drain metallic layer including a source electrode and a drain electrode not contacted with each other; a conductive protection layer formed on the substrate on which the first passivation metallic protection layer has been formed; and a pixel electrode formed on the substrate on which the conductive protection layer has been formed, the pixel electrode contacting the conductive protection layer.

Methods of fabricating a thin-film transistor are provided. The methods include forming a gate electrode above a substrate, a gate insulating layer above the gate electrode, a non-crystalline silicon layer above the gate insulating layer, and a channel protective layer above the non-crystalline silicon layer. The non-crystalline silicon layer and the channel protective layer are processed to form a projecting part. The projecting part has an upper layer composed of the channel protective layer and a lower layer composed of the non-crystalline silicon layer. The projecting part and portions of the non-crystalline silicon layer on sides of the projecting part are irradiated with a laser beam to crystallize at least the non-crystalline silicon layer in the projecting part. An absorptance of the non-crystalline silicon layer for the laser beam is greater in the projecting part than in the portions on the sides of the projecting part.

Embodiments of the present invention disclose a thin film transistor and an array substrate, manufacturing methods thereof, and a display device, which relate to the field of display technology, and can improve drifting of a threshold voltage of a thin film transistor and enhance the stability and reliability of an array substrate. The thin film transistor comprises an active layer and a gate insulating layer, wherein the material of the active layer is a metal oxide semiconductor, and during forming the thin film transistor, the gate insulating layer conveys oxygen to the active layer so as to reduce an interface state density and a movable impurity concentration of a. contact interface between the active layer and the gate insulating layer.

When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 110.sup.13 atoms/cm.sup.2 or lower.

An enhancement-depletion circuit element includes a depletion-mode load transistor and an enhancement-mode drive transistor formed from the common elements of: a first patterned conductive layer including a load gate electrode and a drive gate electrode; a patterned inorganic dielectric stack including a load gate dielectric and a drive gate dielectric; a patterned inorganic semiconductor layer including a load semiconductor region and a drive semiconductor region; a second patterned conductive layer including a load source, a load drain, a drive source and a drive drain; and a patterned differential passivation structure having a patterned polymer dielectric layer and a patterned conformal inorganic dielectric layer. The depletion-mode load transistor has a load back-channel in contact with the patterned conformal inorganic dielectric layer. The enhancement-mode drive transistor has a drive back-channel in contact with the patterned polymer dielectric layer.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.

Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.

A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor (MOS) active layer, a source electrode and a drain electrode on a substrate. The MOS active layer includes forming a pattern layer of indium oxide series binary metal oxide including a first, second, and third pattern directly contacting with the source electrode and the drain electrode. An insulating layer formed over the source electrode and the drain electrode acts as a protection layer, the pattern layer of indium oxide series binary metal oxide is implanted with metal doping ions by using an ion implanting process, and is annealed, so that the indium oxide series binary metal oxide of the third pattern is converted into the indium oxide series multiple metal oxide to form the MOS active layer.