Patent classifications
H10D30/6704
SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.
Method for manufacturing semiconductor device and manufacturing apparatus of semiconductor device
A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to 60 C., preferably with a dew point of lower than or equal to 75 C. without exposing the first substrate after the heat treatment to the air; and then, the first substrate is bonded to a second substrate that serves as an opposite substrate.
TRANSISTOR AND DISPLAY DEVICE
It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
Semiconductor device and method for manufacturing semiconductor device
A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.
SEMICONDUCTOR DEVICE
To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.
Method of manufacturing a semiconductor device to prevent occurrence of short-channel characteristics and parasitic capacitance
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic appliance including the semiconductor device, the display device, and the display module
In a semiconductor device including a transistor, the transistor is provided over a first insulating film, and the transistor includes an oxide semiconductor film over the first insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the oxide semiconductor film and the gate electrode, and a source and a drain electrodes electrically connected to the oxide semiconductor film. The first insulating film includes oxygen. The second insulating film includes hydrogen. The oxide semiconductor film includes a first region in contact with the gate insulating film and a second region in contact with the second insulating film. The first insulating film includes a third region overlapping with the first region and a fourth region overlapping with the second region. The impurity element concentration of the fourth region is higher than that of the third region.
Semiconductor device, memory device, electronic device, or method for driving the semiconductor device
A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor are electrically connected to a first terminal of a capacitor, and a control circuit is electrically connected to a second terminal of the capacitor. The control circuit supplies a first potential to the second terminal of the capacitor, in other words, adds a value corresponding to the first potential to the value of first data previously retained in the gate of the second transistor in order to obtain second data. In the second transistor, the second data, specifically, a third potential commensurate with the potential of the gate will be output from a second terminal when a second potential is supplied to a first terminal.