The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a gate, a gate insulation layer, a first semiconductor layer, an etch stop layer and a second semiconductor layer sequentially stacked on a surface of the substrate, and a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively. A first via and a second via are formed on the etch stop layer corresponding to the source and the drain respectively. The source connects the first semiconductor layer through the first via; the drain connects the first semiconductor layer through the second via. The thin film transistor of the disclosure can effectively increase the on-state current of the thin film transistor and have a faster switching speed.

A thin film transistor (TFT) substrate in which properties of a TFT may be modified according to a function of the TFT, a display apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the display apparatus. The thin film transistor (TFT) substrate includes a substrate; a first TFT disposed on the substrate and comprising a first active pattern and a first gate electrode at least partially overlapping with the first active pattern and disposed between the substrate and the first active pattern; and a second TFT disposed on the substrate and comprising a second active pattern and a second gate electrode at least partially overlapping with the second active pattern.

The present invention provides an array substrate and a manufacturing method thereof and a liquid crystal display panel using the array substrate. The array substrate includes: a first substrate (32), a gate line formed on the first substrate (32), a data line (34) formed on the first substrate (32), a thin-film transistor array formed on the first substrate (32), a pixel electrode (36) formed on the thin-film transistor array, a first passivation layer (38) formed on the pixel electrode (36), the data line (34), and the thin-film transistor array, a black matrix (42) formed on the first passivation layer (38), and a common electrode (44) formed on the black matrix (42) and the first passivation layer (38). The present invention arranges the black matrix formed on the array substrate to reduce the parasitic capacitance between the common electrode and the gate line and the data line so as to help enhance uniformity of voltage on the common electrode.

A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200 C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate. The part (P) of the drain electrode (9d) includes the first drain metal layer (9d1) and does not include the second drain metal layer (9d2).

The present invention discloses a thin-film transistor and a fabricating method thereof, an array substrate and a display apparatus. An active layer in the thin-film transistor comprises a first active layer and a second active layer which are stacked; wherein, an orthographic projection of the first active layer on the substrate covers orthographic projections of the source electrode, the drain electrode as well as a gap located between the source electrode and the drain electrode on the substrate, and covers an orthographic projection of the gate electrode on the substrate; the second active layer is located at the gap between the source electrode and the drain electrode, and an orthographic projection of the second active layer on the substrate is located in a region where the orthographic projection of the gate electrode on the substrate is located.

The process of fabricating a flexible TFT back-panel includes depositing etch stop material on a glass support. A matrix of contact pads, gate electrodes and gate dielectric are deposited overlying the etch stop material. Vias are formed through the dielectric in communication with each pad. A matrix of TFTs is formed by depositing and patterning metal oxide semiconductor material to form an active layer of each TFT overlying the gate electrode. Source/drain metal is deposited on the active layer and in the vias in contact with the pads, the source/drain metal defining source/drain terminals of each TFT. Passivation material is deposited in overlying relationship to the TFTs. A color filter layer is formed on the passivation material and a flexible plastic carrier is affixed to the color filter. The glass support member and the etch stop material are then etched away to expose a surface of each of the pads.

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.