A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.

A manufacturing method of a display panel includes following steps: forming a semiconductor layer on a substrate, in which the semiconductor layer includes a semiconductor sub-layer and an ohmic contact layer including a first sub-ohmic contact layer and a second sub-ohmic contact layer, and a volume flow rate of phosphine for forming the first sub-ohmic contact layer is greater than or equal to 6590 sccm and less than or equal to 12590 sccm, and a volume flow rate of phosphine for forming the second sub-ohmic contact layer is greater than or equal to 21000 sccm and less than or equal to 27000 sccm.

A driving substrate is provided. The driving substrate includes a substrate and a first metal layer disposed thereon. The first metal layer has a first portion, a second portion, and a third portion, in a top view, the first portion and the second portion are arranged along a first direction, and the third portion extends along the first direction and is connected between the first portion and the second portion. In a second direction perpendicular to the first direction, a width of the third portion is less than both a width of the first portion and a width of the second portion. The driving substrate includes a second metal layer disposed on the substrate and overlapped with the first portion and the second portion; and a semiconductor disposed on the substrate. The first metal layer, the second metal layer, and the semiconductor are overlapped with each other.

An array substrate includes a base substrate, an active layer, a first electrode layer, a first insulating layer, and a second electrode layer sequentially disposed, and a sum of an orthographic projection of the first electrode layer on the base substrate and an orthographic projection of the second electrode layer on the base substrate covers an orthographic projection of the active layer on the base substrate.

Disclosed are a semiconductor comprising amorphous tellurium oxide, thin film transistor and method of fabricating same. In detail, a semiconductor comprising a chalcogen atom comprising at least one selected from the group consisting of a sulfur atom (S) and a selenium atom (Se); and tellurium composite comprising a tellurium (Te) atom and tellurium oxide. A thin film transistor (TFT) fabricated based on the TeO.sub.x channel layer according to the present disclosure exhibits excellent output/transfer characteristics and superior electrical performance with high hole field-effect mobility and a high on/off current ratio of 10.sup.7.

The present inventive concept relates to an atomic layer deposition (ALD) method for forming an IGZO channel layer of a transistor device the method comprising: a deposition cycle step of performing a deposition cycle for depositing an IGZO channel layer on a substrate; and a repeat step of repeatedly performing the deposition cycle step until the IGZO channel layer is formed with a predetermined thickness, wherein in the deposition cycle step, the IGZO channel layer is formed by performing an indium oxide sub-cycle for depositing indium oxide (InO), a gallium oxide sub-cycle for depositing gallium oxide (GaO), and a zinc oxide sub-cycle for depositing zinc oxide (ZnO).

An electronic device includes a scan line, an active element, an internal short-circuit ring, an electrostatic protection element. The active element is disposed in an active area and electrically connected to the scan line. The internal short-circuit ring is disposed in a peripheral area and surrounds the active area. The electrostatic protection element is disposed in the peripheral area and electrically connected to the internal short-circuit ring and the scan line. The electrostatic protection element is a transistor and includes a gate electrode, first and second source/drain electrodes, and a semiconductor layer. The gate electrode is in a floating state, the first source/drain electrode is coupled to the internal short-circuit ring, the second source/drain electrode is coupled to the scan line. A first parasitic capacitance between the gate electrode and the first source/drain electrode is greater than a second parasitic capacitance between the gate electrode and the second source/drain electrode.

Provided are a thin-film transistor and a manufacturing method thereof, and a display substrate, belonging to the technical field of thin-film transistors. The thin-film transistor includes: a base substrate; a gate electrode on the base substrate; an active layer on a side of the gate electrode away from the base substrate, an orthographic projection of the active layer onto the base substrate overlapping with an orthographic projection of the gate electrode onto the base substrate; and a first electrode and a second electrode on a side of the active layer away from the base substrate, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode. Specifically the active layer includes a channel region corresponding to a gap between the first electrode and the second electrode, and a width direction of the channel region is perpendicular or substantially perpendicular to an extending direction of the gate electrode. According to the embodiments of the present disclosure, the illumination stability of the thin-film transistor can be improved without reducing the transmittance of the substrate.

The present disclosure provides a thin film transistor, a preparation method thereof, and a display panel. The thin film transistor includes an active layer and a first gate electrode located on a base substrate, the active layer includes a first film layer and a second film layer stacked on the base substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer includes oxygen element, the second film layer includes crystalline oxide, and the first film layer and the second film layer are formed via synchronous annealing. This approach not only prevents the thin film transistor channel from conducting due to insufficient oxygen content in the second film layer but also avoids issues such as etching residues caused by difficulties in etching the second film layer due to excessive oxygen content during the etching process.

This disclosure provides a communication device and a manufacturing method thereof. The manufacturing method of the communication device includes the following steps: providing a first dielectric layer, wherein the first dielectric layer includes a first region and a second region, and the first dielectric layer has a first surface and a second surface opposite to the first surface; providing a second dielectric layer; combining the first dielectric layer and the second dielectric layer with a sealing element, so that the sealing element is disposed between the first surface of the first dielectric layer and a third surface of the second dielectric layer; after combining the first dielectric layer and the second dielectric layer, thinning the second surface of the first dielectric layer; and disposing a first communication element on the first surface of the first dielectric layer in the first region.