A TFT substrate and a method for manufacturing the TFT substrate are provided. A TFT structure is formed on a substrate. A color resist layer is formed on the substrate, and a first opening area is formed in the color resist layer at a location corresponding to the TFT structure. A first black matrix is formed in the first opening area such that the TFT structure is covered by the first black matrix. A pixel electrode is formed on the color resist layer and the first black matrix and is electrically coupled to the TFT structure through the first black matrix. With such an arrangement, light can be shielded and light transmittance can be reduced when a panel including the TFT substrate is bent. This helps improve contrast of the panel.

A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

An array substrate, a display panel, and a fabrication method of the array substrate are provided. The array substrate comprises a first thin film transistor including a metal oxide thin film transistor, and a second thin film transistor including an amorphous silicon thin film transistor. The first thin film transistor and the second thin film transistor are disposed above a substrate. The first thin film transistor is located in a display region of the array substrate, and the second thin film transistor is located in a peripheral circuit region of the array substrate.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Embodiments of the disclosure provide a thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device. The thin film transistor comprises a substrate (1), and a gate electrode (2), a source electrode (41) and a drain electrode (42) provided on the substrate. A projection of a gap between the source electrode (41) and the drain electrode (42) on the substrate (1) coincides with a projection of the gate electrode (2) on the substrate (1).

The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably.

The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

A thin film transistor includes a gate electrode including a gate pattern positioned on a substrate and a gate clad pattern covering the gate pattern. An oxide semiconductor layer is positioned on the gate electrode. A source electrode and a drain electrode are positioned on the oxide semiconductor layer. The source electrode and the drain electrode are ach in contact with end portions of the oxide semiconductor layer.

The thin film transistor (TFT) contains a gate electrode metallic layer above a substrate, a gate insulator layer covering the substrate and the gate electrode metallic layer, a first source electrode metallic layer and a first drain electrode metallic layer above the gate insulator layer and separated by a gap, an active layer above the first source and first drain electrode metallic layers filling the gap and forming a ditch in the active layer above the gap, and a second source electrode metallic layer and a second drain electrode metallic layer above the active layer at two lateral sides of the ditch, respectively. The second source/drain electrode metallic layer contacts the first source/drain electrode metallic layer. The TFT has lower parasitic capacitance and takes up less area. As such, when the TFT is applied to a LCD, the reduced space consumed by the TFT enhances pixel's aperture ratio.