The present invention provides a pixel structure, comprising scan lines, data lines and pixel areas, and the scan lines are separately arranged in parallel along a horizontal direction, and the data lines are separately arranged in parallel along a vertical direction, and the scan lines and the data lines overlap with each other to form the pixel areas, and the pixel structure further comprises a connection electrode employed to coupled to pixel areas, and the connection electrode comprises a first connection layer and a second connection layer, and the first connection layer is in the same pattern layer with the scan lines and intersects with the scan lines, and the first connection layer at an intersecting position with the scan line is disconnected, and the second connection layer is in the same pattern layer with the data lines and crosses with the scan lines.

An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.

An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.

The present invention provides a TFT substrate structure and a manufacturing method thereof. In the manufacturing method of a TFT substrate structure according to present invention, a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer, wherein the modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone; portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserves the excellent electrical conduction property of graphene and thus electrical connection between the source and drain electrodes and the semiconductor layer can be achieved without formation of a via in the graphene layer, making a TFT device so manufactured showing excellent I-V (current-voltage) output characteristics and stability, saving one mask operation process, shortening the manufacturing time, and lowering down the manufacturing cost.

A thin film transistor, a manufacturing method thereof and an array substrate are provided. The thin film transistor comprises: a gate electrode (11), a source electrode (15) and a drain electrode (16), and the thin film transistor further comprises a buffer layer (11) which is directly provided at one side or both sides of at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16), wherein, the buffer layer (11) and at least one of the gate electrode (11), the source electrode (15) and the drain electrode (16) directly contacting the buffer layer (11) are conformal. Therefore, the adhesion between an electrode of the thin film transistor and a film layer contacting it is improved and at the same time an atom in the electrode of the thin film transistor is effectively prevented from diffusing to the film layer connected with it, and the reliability of the thin film transistor is improved and the production cost is reduced.

The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an active layer of the TFT corresponding to a gap between a source electrode and a drain electrode includes a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer. The source electrode and the drain electrode are directly lapped onto the active layer.

The present disclosure relates to an array substrate, a method for manufacturing the array substrate and a display panel. The array substrate includes: a substrate; a poly-silicon thin film disposed on the substrate and including grains arranged along a first direction and a second direction, wherein grain boundaries of the grains extend along the first direction and the second direction; and a plurality of thin film transistors each including a channel formed by the poly-silicon thin film, wherein the channel includes a plurality of intersecting channel portions, each of which extends along a direction that neither perpendicular to nor parallel with the first or second direction.

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3), a semiconductor-layer thin film (4) and a passivation-shielding-layer thin film (5) successively; forming a pattern (5) that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c) and a drain electrode (4b). The source electrode (4c) and the drain electrode (4b) are disposed on two sides of the active layer (4a) respectively and in a same layer as the active layer (4a). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.

The present disclosure relates to a new generation of laser-crystallization approaches that can crystallize Si films for large displays at drastically increased effective crystallization rates. The particular scheme presented in this aspect of the disclosure is referred to as the advanced excimer-laser annealing (AELA) method, and it can be readily configured for manufacturing large OLED TVs using various available and proven technical components. As in ELA, it is mostly a partial-/near-complete-melting-regime-based crystallization approach that can, however, eventually achieve greater than one order of magnitude increase in the effective rate of crystallization than that of the conventional ELA technique utilizing the same laser source.