According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.

According to one embodiment, when a wafer is placed on a base stand and a first frequency voltage is applied to the base stand, the potential of the wafer is measured, and the first frequency voltage is applied in a pulsed manner to the base stand and a base stand voltage is applied to the base stand, and the amplitude of the base stand voltage is controlled based on the potential of the wafer in synchronization with the timing for a pulse waveform cf the first frequency voltage.

According to the embodiment, a semiconductor device includes: a stacked body; a columnar portion, an insulating portion; and wall portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion is provided in the stacked body and extends in a staking direction of the stacked body. The insulating portion is provided around the stacked body and surrounds the stacked body. The wall portion is provided in the insulating portion and is separated from the stacked body. The wall portion extends in the stacking direction and in a first direction crossing the stacking direction.

In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.

According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.

A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device.

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

Nonvolatile memory devices includes a charge storage element having a MOS capacitor structure and including a control gate terminal connected to a word line and a body terminal connected to a body bias line, a first half-MOS transistor having a first selection gate terminal connected to the word line and a first impurity junction terminal connected to a bit line and sharing the body terminal with the charge storage element, and a second half-MOS transistor having a second selection gate terminal connected to the word line and a second impurity junction terminal connected to a source line and sharing the body terminal with the charge storage element. The charge storage element is coupled between the first and second half-MOS transistors so that the first half-MOS transistor, the charge storage element, and the second half-MOS transistor are connected in series.