The present invention relates to a process of fabricating P(VDF-TrFE) films by modifying the solvent composition. Two solvents MEK and DMSO were mixed in pre-determined ratios and that co-solvent mixture was used for fabricating the P(VDF-TrFE) films. By virtue of such method driven P(VDF-TrFE) films, the ferroelectric capacitors comprising of the same were found to achieve low voltage operation, thermal stability and fatigue endurance, which indicated improved ferroelectric performance of the devices. In addition, the films made by same process also yielded high piezo- and pyro-electric coefficient, indicating improved piezo- and pyro-electric performances of the devices.

A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.

A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. The semiconductor device may include second channel layers adjacent to the first channel layers in a second direction crossing the first direction and arranged in the first direction. The semiconductor device may include insulating layers stacked while surrounding side walls of the first and second channel layers. The semiconductor device may include conductive layers interposed between the insulating layers, and including first metal patterns extended in the first direction and second metal patterns extended in the first direction while surrounding the side walls of the first channel layers.

A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

According to one embodiment, a first semiconductor body extends in a stacking direction of a stacked body through a first stacked unit and contacts a foundation layer. A plurality of contact vias extend in the stacking direction through an insulating layer and contact a plurality of terrace portions. A second semiconductor body extends in the stacking direction through a second stacked unit. An insulating film is provided between the foundation layer and a lower end portion of the second semiconductor body.

A semiconductor memory device according to one embodiment includes a substrate, a stacked body provided on a first-direction side of the substrate, a semiconductor member extending in the first direction, and a charge storage film provided between the stacked body and the semiconductor member. The stacked body includes first insulating films and electrode films stacked alternately along the first direction. A recess is made in a surface of the stacked body facing the semiconductor member every one of the electrode films.

A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

A semiconductor memory device according to one embodiment includes a stacked body, a semiconductor pillar and a plurality of charge storage films. The stacked body includes a plurality of electrode films and air gaps. The plurality of electrode films are disposed to be separated from each other along a first direction. Each of the air gaps is made between the electrode films. The semiconductor pillar extends in the first direction and pierces the stacked body. The plurality of charge storage films are provided between the semiconductor pillar and the plurality of electrode films. The plurality of charge storage films are partitioned every electrode film.