A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.

The flash memory includes a stacked gate disposed on a substrate. The stacked gate includes an erase gate and two floating gates. Each floating gate has an acute angle pointing toward the erase gate. There is a high electric field formed around the acute angle so that the flash memory can perform an erase mode even at a lower operational voltage. Furthermore, the flash memory does not use any control gate to perform a write mode.

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

A semiconductor structure includes a substrate including a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a control gate structure disposed over the first doped region and electrically connected to a control bit line; a fuse gate structure disposed over the second doped region and electrically connected to a fuse bit line; and a buried word to line disposed between the control gate structure and the fuse gate structure, wherein the buried word line is disposed within the recess of the substrate.

Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided.

According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance changeable layer, an oxygen reservoir layer and a reactive oxygen barrier layer. The bottom electrode is disposed on a substrate. The top electrode is disposed above the bottom electrode. The resistance changeable layer is disposed between the bottom electrode and the top electrode. The oxygen reservoir layer is disposed between the resistance changeable layer and the top electrode. The reactive oxygen barrier layer is disposed inside the oxygen reservoir layer.

A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.