According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, columnar portions, and first and second interconnection portions. The stacked body includes insulating layers and electrode layers alternately stacked one layer by one layer on the substrate. The columnar portions are provided between the first and second interconnection portions and include a first row having a first columnar portion and a second row having a second columnar portion, the first columnar portion being positioned closest to the first interconnection portion, and the second columnar portion being positioned closest to the second interconnection portion. A distance between the first interconnection portion and the first columnar portion is smaller than a distance between the second interconnection portion and the second columnar portion, and the distance between the second interconnection portion and the second columnar portion is greater than 20 nanometers.

According to an embodiment, a semiconductor memory device includes a substrate, at least one stacked body, and a first insulating film. The stacked body includes a first end portion positioned at an end in at least one of a first direction and a second direction that crosses the first direction along a surface of the substrate, the plurality of electrode layers being formed into stairs in the first end portion, each of the plurality of electrode layers having a step in the first end portion. The first insulating film is provided on the substrate and includes first and second surfaces, the first and second surfaces surrounding the first end portion, the first surface being crossing a direction that the steps are formed, the second surface being positioned along the direction that the steps are formed.

A semiconductor memory device includes a plurality of first electrode layers stacked in a first direction; a semiconductor layer extending in the first direction in the plurality of first electrode layers; a first insulating layer extending in the first direction along the semiconductor layer between the semiconductor layer and each of the plurality of first electrode layers; a second insulating layer covering the periphery of the plurality of first electrode layers; a resistive body provided on the second insulating layer; and a third insulating layer provided between the resistive body and the second insulating layer, the third insulating layer including the same material as the material of the first insulating layer.

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type; a stacked body; a plurality of columnar portions; a plurality of first insulating portions having a wall configuration; and a plurality of second insulating portions having a columnar configuration. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body and a charge storage film. The first insulating portions extend in the stacking direction and in a first direction crossing the stacking direction. The second insulating portions extend in the stacking direction. A wide of the second insulating portions along a second direction crossing the first direction in a plane is wider than a wide of the first insulating portions along the second direction. The second insulating portions are disposed in a staggered lattice configuration.

A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.

To provide a semiconductor device with excellent charge retention characteristics, a transistor including a thick gate insulating film to achieve low leakage current is additionally provided such that its gate is connected to a node for holding charge. The node is composed of this additional transistor and a transistor using an oxide semiconductor in its semiconductor layer including a channel formation region. Charge corresponding to data is held at the node.

A non-volatile memory having memory cells is provided. The memory cells include stack structures, floating gates, tunneling dielectric layers, erase gate dielectric layers, auxiliary gate dielectric layers, source regions, drain regions, control gates and inter-gate dielectric layers. The stacked structures include gate dielectric layers, auxiliary gates, insulating layers and erase gates. The floating gates are disposed on sidewalls on a first side of the stacked structures. The tunneling dielectric layers are disposed under the floating gates. The erase gate dielectric layers are disposed between the erase gates and floating gates. The auxiliary gate dielectric layers are disposed between the auxiliary gates and the floating gates. The source and drain regions are separately disposed on sides of the stack structures and the floating gates. The control gates are disposed on the source regions and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.

A semiconductor memory device having one embodiment which includes a substrate; a stacked body provided on the substrate and including a plurality of electrode layers separately stacked; a first upper layer gate provided on the stacked body; an interlayer insulating layer provided on the first upper layer gate; an insulating part continuously provided from the first upper layer gate to the substrate and extending in a first direction parallel to a major surface of the substrate; a second upper layer gate; a semiconductor part; a charge storage film; and a semiconductor layer provided from an upper end of the semiconductor part to a portion of the semiconductor part reaching the second upper layer gate. The second upper layer gate is provided on the interlayer insulating layer and the insulating part, and extends on a first surface parallel to the major surface.

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body; a first columnar portion; a second columnar portion; and a plurality of first interconnects. The stacked body is provided on the substrate and includes a plurality of electrode layers separately stacked each other. A distance between the first columnar portion and one end of the plurality of electrode layers in the first direction is smaller than a distance between the second columnar portion and the other end of the plurality of electrode layers in the first direction. In the same electrode layer, a first width of a first charge storage film of the first columnar portion is smaller than a second width of a second charge storage film of the second columnar portion.

According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.