An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.

A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.

A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

A memory device includes a multi-layer stack. The multi-layer stack is disposed on a substrate and includes a plurality of first conductive lines and a plurality of dielectric layers stacked alternately, wherein each of the plurality of first conductive lines has a first side and a second side opposite to the first side. The memory device further includes a plurality of second conductive lines crossing over the plurality of first conductive lines, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become far away from the first side.

According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; first and second insulating layers in contact with the first semiconductor layer; a second semiconductor layer in contact with the first insulating layer; a third semiconductor layer in contact with the second insulating layer; a first conductor; a third insulating layer in contact with the first conductor; a fourth insulating layer provided between the second semiconductor layer and the third insulating layer; a first charge storage layer provided between the second semiconductor layer and the fourth insulating layer; and a fifth insulating layer provided between the second semiconductor layer and the first charge storage layer. The second semiconductor layer, the first conductor, the third to fifth insulating layers, and the first charge storage layer function as a first memory cell.

Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.

Memory openings and support openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. The support openings are laterally expanded by laterally recessing the insulating layers with respect to the sacrificial material layers. The laterally expanded support openings are filled with a combination of a dielectric material and a sacrificial fill material to form support pillar structures. After forming memory films and channels in the memory openings, the sacrificial material layers are replaced with electrically conductive layers while the support pillar structures provide structural support to the insulating layers. The sacrificial fill material is replaced with contact via structures to form integrated support and contact structures.

Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.