A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.

A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.

Provided is an etching method for simultaneously etching first and second regions of a workpiece. The first region has a multilayered film configured by alternately laminating a silicon oxide film and a silicon nitride film and a second region has a silicon oxide film having a film thickness that is larger than that of the silicon oxide film in the first region. A mask is provided on the workpiece to at least partially expose each of the first and second regions. In the etching method, plasma of a first processing gas containing fluorocarbon gas, hydrofluorocarbon gas, and oxygen gas is generated within a processing container of a plasma processing apparatus. Subsequently, plasma of a second processing gas containing fluorocarbon gas, hydrofluorocarbon gas, oxygen gas, and a halogen-containing gas is generated within the processing container. Subsequently, plasma of a third processing gas containing oxygen gas is generated within the processing container.

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

A semiconductor memory device includes a conductive layer on a source side; a first electrode layer provided on the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a semiconductor layer extending through the first electrode in a first direction from the conductive layer to the first electrode layer; a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body including first impurities; and a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body. A diffusion coefficient of the second impurities in the second semiconductor body is smaller than a diffusion coefficient of the second impurities in the first semiconductor body.

Memory-opening semiconductor material portions and support opening fill structures can be simultaneously formed through a first alternating stack of first insulating layers and first sacrificial material layers. Dopant species that retard or prevent etching of the material of the support opening fill structures can be implanted into an upper portion of each support opening fill structure, while memory-opening semiconductor material portions are masked from implantation. After formation of a second alternating stack and second openings therethrough, the sacrificial material of the memory-opening semiconductor material portions is removed while the support opening fill structures is not removed. Damage to the first sacrificial material layers during formation of the staircase contact region and resulting leakage paths from word lines to the substrate through support pillar structures can be avoided or reduced by not removing the support opening fill structures.

The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.

A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.