A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising In.sub.iGa.sub.1-iAs with an Indium content i with a slope s1 and a second base layer on the emitter side comprising In.sub.iGa.sub.1-jAs with an Indium content j with a slope s2, and an average of s1 is half of the average of s2 or smaller; or the base comprises a first base layer comprising In.sub.mGa.sub.1-mAs with an Indium content m and a second base layer on the emitter side comprising In.sub.nGa.sub.1-nAs with an Indium content n, and an average of n is larger than the m at a second base layer side; or the base comprises a first base layer pseudomorphic to GaAs with a bulk lattice constant larger than GaAs, and the emitter comprises a first emitter layer pseudomorphic to GaAs with a bulk lattice constant smaller than GaAs.

A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.

An ITC-IGBT and a manufacturing method therefor. The method comprises: providing a heavily doped substrate, forming a Ge.sub.xSi.sub.1-x/Si multi-quantum well strained super lattice layer on the surface of the heavily doped substrate, and forming a lightly doped layer on the surface of the Ge.sub.xSi.sub.1-x/Si multi-quantum well strained super lattice layer. The Ge.sub.xSi.sub.1-x/Si multi-quantum well strained super lattice layer is formed on the surface of the heavily doped substrate through one step, simplifying the production process of the ITC-IGBT.

A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity. Also, thermal shunts are disposed on the substrate between adjacent transistor fingers, where the thermal shunts are electrically isolated from the transistor fingers.

To manufacture a bipolar transistor, a first stack of layers including a first layer made of the material of the base of the bipolar transistor is formed between second and third insulating layers. A first cavity is then formed crossing the first stack in such a way as to reach the substrate. The forming of the first cavity includes an etching of no layer covering the first layer other than the third layer. A first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor are then formed in the first cavity.

A bipolar transistor and a method of making a bipolar transistor. The method includes providing a semiconductor substrate having a major surface, one or more layers located beneath the major surface for forming an intrinsic base, and a collector. The method also includes depositing a first oxide layer on the major surface, depositing a second oxide layer on the first oxide layer, and depositing an extrinsic base layer on the second oxide layer. The method further includes forming an emitter window through the extrinsic base layer. The method also includes removing at least a part of the second oxide layer to form a first cavity and forming an initial part of a base link region in the first cavity. The method also includes removing at least a part of the first oxide layer to form a second cavity and filling the second cavity to form a completed base link region.

A process for making a transistor that includes removing a sacrificial material under a base layer that includes dopants for an intrinsic base of a transistor. After the removal of the sacrificial layer to form a cavity directly under the base layer, a semiconductor material is formed in the cavity. The semiconductor layer includes dopants for a current electrode of the transistor that is located directly under the intrinsic base of the transistor.

A bipolar junction transistor has a collector over a substrate, a base over the collector, and an emitter over the base. The base includes a III-V ternary semiconductor alloy including first, second, and third elements, and having a narrower bandgap than a binary semiconductor alloy including only the first and second elements. At least a portion of the base has a differential concentration of the third element such that a concentration of the third element at a first location in the base is greater than at a second location in the base, the second location between the first location and the collector.

A bipolar junction transistor a base over a collector, the base including a III-V ternary semiconductor alloy including first, second, and third elements. The LI-V ternary semiconductor alloy has a narrower bandgap than a binary semiconductor alloy including only the first and second elements. A ledge between an emitter and a base contact being 0.5 m or less.

A bipolar junction transistor has a collector over a substrate and a base structure over the collector, the base including a III-V ternary semiconductor alloy, the base having a base contact formed thereon. An emitter is over the base structure, and a ledge between the emitter structure and the base contact is 0.3 m or less.