Systems, methods and apparatus are provided for a two access device, one storage node memory cell in a vertical three-dimensional memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. The memory cell has a second horizontally oriented access device having a first source/drain region and a second source/drain region separated by a second channel region. The second access device is operatively controlled by a second gate. A shared storage node is coupled between the second source/drain regions of the first access device and the second access device.

To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including agate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

A display apparatus can include a substrate, a pixel driving circuit on the substrate, and a light emitting device connected to the pixel driving circuit. The pixel driving circuit comprises a first thin film transistor, a second thin film transistor, and a third thin film transistor. The first thin film transistor comprises a first active layer and a first gate electrode. The second thin film transistor comprises a second active layer and a second gate electrode. The third thin film transistor comprises a third active layer and a third gate electrode, and the first active layer and the third active layer are disposed under the second active layer.

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is positioned above the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is positioned above the first insulating layer. The semiconductor layer is in contact with the second conductive layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is positioned above the third insulating layer and includes a second opening reaching the third insulating layer in a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.

One embodiment of the present disclosure seeks to provide a thin film transistor and display device comprising: an active layer; a cover insulating film on the active layer; a first cover layer on the cover insulating film; and a gate electrode spaced apart from the active layer and at least partially overlapping the active layer, wherein the first cover layer covers an top surface of the cover insulating film and a side surface of the active layer, and the first cover layer includes an oxide semiconductor material and has a resistivity greater than that of the active layer.

A display substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate. The sub-pixel includes: a data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern including a portion extending along the first direction; and a sub-pixel driving circuit. The sub-pixel driving circuit includes two switching transistors, a driving transistor, and a storage capacitor; a first/second electrode plate of the storage capacitor is coupled to a gate electrode of the driving transistor/the power signal line pattern, second electrodes of the two switching transistors are both coupled to a first electrode of the driving transistor, and orthographic projection of a second electrode of at least one of the two switching transistors on the substrate at least partially overlaps orthographic projection of the power signal line pattern or the second electrode plate on the substrate.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor, a connection portion, a first insulator, a second insulator, and a first wiring. The connection portion includes a first electrode and a second electrode. The first transistor includes the second electrode, a third electrode, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator includes a first opening reaching the first wiring. The first electrode is in contact with a side surface of the first opening and the top surface of the first wiring. The second electrode is in contact with the first electrode in the first opening. The second insulator includes a second opening reaching the second electrode. The third electrode is provided over the second insulator. The first semiconductor is in contact with the third electrode, a side surface of the second insulator in the second opening, and the top surface of the second electrode. The gate insulator is in contact with the first semiconductor in the second opening. The first gate electrode faces the first semiconductor with the gate insulator therebetween.

A semiconductor device includes a channel including a two-dimensional semiconductor material, a source electrode and a drain electrode electrically connected to both ends of the channel, respectively, a two-dimensional material oxide layer on the channel, a dipole oxide layer on the two-dimensional material oxide layer, a dielectric layer on the dipole oxide layer, and a gate electrode on the dielectric layer.

A semiconductor device that can be reduced in size or highly integrated is provided. The semiconductor device includes first and second transistors and first to third conductors. The first transistor includes first and second gate electrodes between which a semiconductor layer of the first transistor is positioned. The second gate electrode is provided over the semiconductor layer of the first transistor to overlap the first gate electrode. The second transistor includes a third gate electrode over a semiconductor layer of the second transistor. The second transistor is stacked over the first transistor. The third gate electrode overlaps the second gate electrode. The first conductor electrically connects a source electrode of the first transistor and a source electrode of the second transistor. The second conductor electrically connects a drain electrode of the first transistor and a drain electrode of the second transistor. The third conductor electrically connects the first gate electrode, the second gate electrode, and the third gate electrode.

A semiconductor device is provided. The semiconductor device includes: a bit line provided on a substrate and extending along a first horizontal direction; a mold structure provided on the bit line, extending along a second horizontal direction crossing the first horizontal direction, and including a metal layer; an active semiconductor layer extending along a vertical direction on a side wall of the mold structure and including an oxide semiconductor; and a word line provided on a side wall of the active semiconductor layer and extending along the second horizontal direction. At least a portion of the side wall of the active semiconductor layer is in contact with the metal layer.