Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid.

An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.

The present disclosure provides a TFT, a method for manufacturing the same, an array substrate and a display device, so as to effectively reduce a TFT edge leakage current I.sub.OFF (edge). The TFT includes an active layer and a silicon oxide layer arranged at a lateral side of the active layer.

Methods of fabricating a thin-film transistor are provided. The methods include forming a gate electrode above a substrate, a gate insulating layer above the gate electrode, a non-crystalline silicon layer above the gate insulating layer, and a channel protective layer above the non-crystalline silicon layer. The non-crystalline silicon layer and the channel protective layer are processed to form a projecting part. The projecting part has an upper layer composed of the channel protective layer and a lower layer composed of the non-crystalline silicon layer. The projecting part and portions of the non-crystalline silicon layer on sides of the projecting part are irradiated with a laser beam to crystallize at least the non-crystalline silicon layer in the projecting part. An absorptance of the non-crystalline silicon layer for the laser beam is greater in the projecting part than in the portions on the sides of the projecting part.

To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/m or less and off-state current at 85 C. can be 100 aA/m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85 C. can be 100 aA/m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.

A voltage supply device includes a bias generator, a control signal generator and a cell switching circuit. The bias generator divides a first supply voltage to output a plurality of divided supply voltages. The control signal generator receives the plurality of divided supply voltages to generate a plurality of control signals. The cell switching circuit receives the plurality of control signals to provide nonvolatile memory cells with one or more of a ground voltage, the first supply voltage, or a second supply voltage different from the first supply voltage. Each of the bias generator, the control signal generator and the cell switching circuit is implemented with medium voltage MOS transistors having a breakdown voltage of from approximately 7 volts to approximately 15 volts.

The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.910.sup.5 .Math.m or more and 4.810.sup.3 .Math.m or less.

The present invention provides a co-planar oxide semiconductor TFT substrate structure and a manufacture method thereof. In the co-planar oxide semiconductor TFT substrate structure, the active layer comprises a main body and a plurality of short channels connected to the main body, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With forming the plurality of strip metal electrodes between the source and the drain, which are separately positioned, as deposing the oxide semiconductor layer, the plurality of short channels can be formed between the source and the drain. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel fog nation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.