A semiconductor device includes a glass substrate, a base layer on the glass substrate, and a thin film transistor on the base layer, wherein the base layer has a structure in which a first insulating layer made of silicon oxide, a second insulating layer made of silicon nitride, a conductive layer, and a third insulating layer made of silicon oxide are stacked in this order from the glass substrate side. The base layer may have a fourth insulating layer made of silicon oxide between the second insulating layer and the conductive layer.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

A display apparatus including a light-emitting element and a thin-film transistor electrically connected to the light-emitting element is disclosed. In an embodiment, the thin-film transistor includes a substrate, an active layer disposed on the substrate, a gate electrode disposed on the active layer, a buffer layer disposed between the active layer and the substrate. The-film transistor includes a semiconductor structure disposed under at least a portion of the buffer layer and overlapping at least a portion of the active layer from a plan view.

The present description concerns an integrated circuit chip comprising at least one component, arranged inside and/or on top of a structure comprising a semiconductor substrate on which rests an insulating layer having a semiconductor layer resting thereon, wherein at least two PN junctions are arranged at the interface between the substrate and the insulating layer.

A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

An oxide semiconductor film with high carrier mobility is provided. The oxide semiconductor film contains indium and oxygen. The oxide semiconductor film includes a crystal grain. The gallium concentration and the zinc concentration in the oxide semiconductor film are each lower than or equal to 0.1 atomic %. The extension length of a grain boundary in the oxide semiconductor film is greater than or equal to 0 nm and less than or equal to 10000 nm. The extension length of the grain boundary is calculated using a field of view of 90 nm square extracted from a TEM image of the oxide semiconductor film. The oxide semiconductor film has a property of transmitting oxygen in a range higher than or equal to 210.sup.20 atoms/cm.sup.3 and lower than or equal to 110.sup.21 atoms/cm.sup.3 in heat treatment at a heating temperature of 400 C. for a treatment time of 8 hours.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

A device includes a gate electrode and a gate dielectric surrounding the gate electrode. The gate electrode surrounds a nanostructure. The nanostructure includes stacked nanosheets. The gate dielectric is formed by a high-k (HK) material. The HK material covers sidewalls of the gate electrode in a direction aligned to adjacent devices. Portions of the HK material are recessed from the sidewalls and refilled by a dielectric material with a dielectric constant less than the HK material and an electrical isolation capability greater than the HK material. Replacing the HK material over the sidewalls of the gate electrode with the dielectric material enhances electrical isolation between the gate electrode with adjacent contacts. Consequently, it can reduce electrical leakage between metal gate (MG) contacts and metal-to-device (MD) contacts in scaled transistors of an integrated circuit (IC).

Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.