Semiconductor devices and methods of writing information to a memory cell include an n-type transistor connected to a first terminal. The n-type transistor is formed with a low injection-barrier material gate dielectric. A p-type transistor is connected in serial between the n-type transistor and a second terminal. The p-type transistor is formed with a low injection-barrier material gate dielectric. The first and second transistor share a common floating gate and a common output node.

Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j2, the jth sub memory cell is arranged over the j1th sub memory cell.

To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate structure. In a non-volatile semiconductor memory device (1), while each of the memory transistor (MGA1) and the switch transistor (SGA) is made to have a single-layer gate structure, when a selected memory cell (3a) is turned on by applying a high voltage to one end of a memory transistor (MGA1) from a source line (SL) during data programming and applying a low voltage to one end of the switch transistor (SGA) from a bit line (BL1), a voltage drop occurs in a low-concentration impurity extension region (ET2) in the memory transistor (MGA1) between the source line (SL) and the bit line (BL1) to generate an intense electric field, and charge can be injected into the floating gate (FG) by source side injection using the intense electric field.

To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.

To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.

A highly reliable storage device with small data deterioration is provided. The storage device includes a first circuit, a second circuit, a third circuit, and a memory cell. The first circuit has a function of detecting power-on. The second circuit has a function of specifying the address of the memory cell. The third circuit has a function of refreshing the memory cell at the address specified by the second circuit after the first circuit detects power-on. The memory cell preferably includes an oxide semiconductor transistor.

A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.