Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.

Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.

A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.