A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.

A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.

A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator. The second capacitor includes an oxide, an eleventh insulator over the oxide, and a fourth conductor over the eleventh insulator.

A nonvolatile memory device may operate with a logic transistor, which includes a transistor gate formed of a material. The memory device includes a floating gate formed of the material, a first-type fin, and a second-type fin. The first-type fin includes a first-type channel, a first-type source, and a first-type drain. The first-type channel, the first-type source, and the first-type drain have a first conductivity type. The second-type fin includes a second-type channel, a second-type source, and a second-type drain. The second-type source and the second-type drain have the first conductivity type. The second-type channel has a second conductivity type opposite to the first conductivity type. The floating gate is positioned on the first-type channel and the second-type channel.

A nonvolatile memory device may operate with a logic transistor, which includes a transistor gate formed of a material. The memory device includes a floating gate formed of the material, a first-type fin, and a second-type fin. The first-type fin includes a first-type channel, a first-type source, and a first-type drain. The first-type channel, the first-type source, and the first-type drain have a first conductivity type. The second-type fin includes a second-type channel, a second-type source, and a second-type drain. The second-type source and the second-type drain have the first conductivity type. The second-type channel has a second conductivity type opposite to the first conductivity type. The floating gate is positioned on the first-type channel and the second-type channel.

In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j2, the jth sub memory cell is arranged over the j-1th sub memory cell.

Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.