A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.

A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor device comprises: a first active region over a substrate; and a first bit line structure intercepting the first active region at a level that is lower than a top-most surface thereof, the first bit line structure including a barrier liner having a U-profile in a width direction thereof in electrical contact with the first active region.

Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

The present disclosure provides a memory device, and a semiconductor structure and a forming method thereof, which includes: providing a substrate, which includes a plurality of bit line structures, forming a cover layer on each of the bit line structures, forming a first insulating layer and a second insulating layer sequentially on a side wall of each cover layer, and filling a space between second insulating layers of two adjacent bit line structures with a conductive contact layer; tops of the conductive contact layers and the second insulating layers are all lower than surfaces of the cover layers and higher than surfaces of the bit line structures; tops of the first insulating layers are flush with those of the conductive contact layers and the second insulating layers; and etching back the conductive contact layers, to form a capacitor contact hole between cover layers of two adjacent bit line structures.

A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.