Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

An integrated circuit device including a lower electrode on a substrate, the lower electrode including a first lower electrode portion extending in a first direction perpendicular to a top surface of the substrate and including a first main region and a first top region, and a second lower electrode portion extending in the first direction on the first lower electrode portion and including a second main region and a second top region; a first top supporting pattern surrounding at least a portion of a side wall of the first top region of the first lower electrode portion; and a second top supporting pattern surrounding at least a portion of a side wall of the second top region of the second lower electrode portion, and the second lower electrode portion includes a protrusion protruding outward to the second top supporting pattern.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

A semiconductor memory device includes a capacitor on a substrate. The capacitor includes a first electrode, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The second electrode includes a first layer, a second layer, and a third layer. The first layer is adjacent to the dielectric layer, and the third layer is spaced apart from the first layer with the second layer interposed therebetween. A concentration of nickel in the third layer is higher than a concentration of nickel in the first layer.

Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

A semiconductor device with a novel structure is provided. One embodiment of the present invention is a semiconductor device including a memory module. The memory module includes a first memory cell, a first wiring, and a second wiring and a third wiring that include a metal oxide. The first memory cell includes a read transistor and a rewrite transistor. The first wiring includes a region functioning as a back gate of the read transistor and a region where the second wiring functions as a conductor. The second wiring includes a region functioning as a channel formation region of the read transistor, a region functioning as a back gate of the rewrite transistor, and a region where the third wiring functions as a conductor. The third wiring includes a region functioning as a channel formation region of the rewrite transistor and a region functioning as a conductor.

Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.

A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.