A semiconductor memory device includes a substrate extending in a first direction and second direction perpendicular to the first direction, bitline structures arranged on a substrate in the first direction, the bitline structures extending in the second direction, spacer structures disposed on sidewalls of the bitline structures to extend in the second direction, the spacer structures including spacers, which are formed of air or silicon oxide, contact structures disposed between the spacer structures and arranged in the second direction; fence structures filling gaps between the contact structures and between the spacer structures, and pad isolation films isolating the contact structures on the bitline structures, the spacer structures, and the fence structures. The fence structures include first fence liners and second fence liners, which are on the first fence liners and are formed of one of air and silicon oxide, and which overlap with the spacers in the first direction.

The present disclosure provides a capacitor, a semiconductor device, and a method for preparing a capacitor. The semiconductor device includes a plurality of memory cells, at least one of the memory cells including a capacitor. The capacitor includes a first electrode comprising titanium nitride and disposed on a substrate, a dielectric film disposed on the first electrode, a multilayer film disposed on the dielectric film, and a second electrode comprising titanium nitride and disposed on the multilayer film. The method for preparing the capacitor includes forming the first electrode comprising titanium nitride on the substrate, forming a dielectric film on the first electrode, forming the multilayer film on the dielectric film, and forming the second electrode comprising titanium nitride on the multilayer film.

Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows. The transistors on one side of each first isolation stripe and the transistors on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the transistors along the corresponding column. Each capacitor corresponds to one of the transistors and connects the source region of the corresponding transistor.

The present invention relates to the field of semiconductor manufacturing technologies, in particular to a semiconductor device and a method of forming the same. The method of forming the semiconductor device includes the following steps: forming a substrate with a trench, a gate dielectric layer covering an inner wall of the trench, a barrier layer covering a portion of a surface of the gate dielectric layer, and a first gate layer filled on an surface of the barrier layer being disposed in the trench; removing a portion of the barrier layer to form an groove located between the first gate layer and the gate dielectric layer; forming a channel dielectric layer at least covering an inner wall of the groove and a top surface of the first gate layer; and forming a second gate layer at least partially filling an interior of the groove.

An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

Provided is a semiconductor device, including an insulating layer, a transistor located on the insulating layer, and a conductive structure, in which the transistor includes: a source, a channel and a drain arranged in parallel, as well as a gate dielectric layer and a gate structure, in which the gate dielectric layer is located between the gate structure and the channel; the conductive structure covers one sidewall of the channel and is used for grounding; the gate structure is disposed around the other three sidewalls of the channel; and the gate structure and the conductive structure are isolated from each other.

Present invention is related to a semiconductor device with an improved reliability and a method for the same. A method for fabricating a semiconductor device according to an embodiment of the present invention may comprise: forming a plurality of bit line structures over a substrate; forming line-shaped openings between the bit line structures; forming a stopper structure on edges of the line-shaped openings; filling a line pattern in each of the line-shaped openings; forming a plurality of contact plugs and a plurality of isolation grooves by etching the line patterns; and filling a plug isolation layer in the isolation grooves.