The disclosure provides a method for manufacturing a memory and the memory. The method includes that a laminated structure is formed on a substrate, in which the laminated structure comprises sacrificial layers and supporting layers arranged alternately, a top layer of the laminated structure is a supporting layer, and a supporting layer between two sacrificial layers is provided with intermediate holes filled with a sacrificial material; capacitor holes penetrating through the laminated structure are formed; a first polar plates are formed on the hole walls and the hole bottoms of the capacitor holes; areas corresponding to the intermediate holes in the supporting layer located on the top layer of the laminated structure are removed to form capacitor opening holes, which exposes a sacrificial layer; and all the sacrificial layers and all the sacrificial material are removed through the capacitor opening holes.

A semiconductor device includes a transistor, a bit line and a bit-line via structure. The transistor is located in a transistor layer, and has a source contact and a drain contact. The bit line is electrically connected to one of the source contact and the drain contact. The bit-line via structure is located in the transistor layer, and electrically interconnects the bit line and a periphery device.

A first impurity layer 101a and a second impurity layer 101b are formed on a substrate Sub at both ends of a Si pillar 100 standing in a vertical direction and having a circular or rectangular horizontal cross-section. Then, a first gate insulating layer 103a and a second gate insulating layer 103b surrounding the Si pillar 100, a first gate conductor layer 104a surrounding the first gate insulating layer 103a, and a second gate conductor layer 104b surrounding the second gate insulating layer 103b are formed. Then, a voltage is applied to the first impurity layer 101a, the second impurity layer 101b, the first gate conductor layer 104a, and the second gate conductor layer 104b to generate an impact ionization phenomenon in a channel region 102 by current flowing between the first impurity layer 101a and the second impurity layer 101b. Of generated electrons and positive holes, the electrons are discharged from the channel region 102 to perform a memory write operation for holding some of the positive holes in the channel region 102, and the positive holes held in the channel region 102 are discharged from one or both of the first impurity layer 101a and the second impurity layer 101b to perform a memory erase operation.

Embodiments of the present application provide a memory structure and a memory layout. The memory structure includes: memory arrays, each including memory cells; read-write conversion circuits, each disposed between two adjacent ones of the memory arrays in a first direction, the read-write conversion circuits being arranged in a second direction, having a symmetry axis in the second direction, and configured to write external data into the memory cells, or read data from the memory cells, and the first direction being perpendicular to the second direction; and sense amplification circuits, symmetrically disposed between two adjacent ones of the memory arrays based on the symmetry axis, and coupled to the memory cells in the adjacent ones of the memory arrays, configured to sense voltages of the memory cells and output logic 1 or 0 corresponding to the voltages of the memory cells.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors.

Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

The embodiments of the present disclosure provide an etching method, an air-gap dielectric layer, and a dynamic random-access memory. The etching method is configured to selectively etch a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film. In addition, the etching method includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate. In the etching method according to the present disclosure, through selectively etching the silicon oxide film, a substantial degradation of an etching selectivity ratio of SiO.sub.2/SiN caused by the surface modification layer on the wafer surface can be avoided. Through making the first etching rate smaller than the second etching rate, a highly efficient etching process is ensured and at the same time, excessive etching can be avoided in the surface layer removal process, thereby further ensuring the high etching selectivity ratio.

A semiconductor device in which variation of characteristics is small is provided. A second insulator, an oxide, a conductive layer, and an insulating layer are formed over a first insulator; a third insulator and fourth insulator are deposited to be in contact with the first insulator; a first opening reaching the oxide is formed in the conductive layer, the insulating layer, the third insulator, and the fourth insulator; a fifth insulator, a sixth insulator, and a conductor are formed in the first opening; a seventh insulator is deposited over the fourth insulator, the fifth insulator, and the sixth insulator; a mask is formed in a first region over the seventh insulator in a top view; oxygen is implanted into a second region not overlapping the first region in the top view; heat treatment is performed; a second opening reaching the fourth insulator is formed in the seventh insulator; and heat treatment is performed.

A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

A microelectronic device comprises memory cell structures extending from a base material. At least one memory cell structure of the memory cell structures comprises a central portion in contact with a digit line, extending from the base material and comprising opposing arcuate surfaces, an end portion in contact with a storage node contact on a side of the central portion, and an additional end portion in contact with an additional storage node contact on an opposite side of the central portion. Related microelectronic devices, electronic systems, and methods are also described.