An image processing device includes an image sensor including a pixel array that includes a first pixel group, and a correlated double sampling circuit. The first pixel group includes a first plurality of normal pixels, a second plurality of normal pixels, and at least one first phase detection pixel. The correlated double sampling circuit is configured to generate first video data, based on charges of the first plurality of normal pixels, generate second video data, based on charges of the second plurality of normal pixels, and generate first phase detection data, based on an output of the at least one first phase detection pixel. The image processing device further includes an image signal processor configured to apply a first weight to the generated first video data, and apply a second weight to the generated second video data.

In some embodiments, a method is performed at a device with a processor, non-transitory memory, and an event camera including pixel sensors distributed across an area. The method includes converting an event stream from a pixel sensor over a first time period into event frames by dividing the first time period into sub-periods, and binning pixel events of the event stream, where each of the sub-periods is associated with a frame sub-period identifier. The method further includes addressing the pixel sensors by sub-dividing the area into tiles, where each of the tiles includes a grouping of the pixel sensors, and a tile address of a particular pixel sensor is a combination of a tile identifier and a position locator of the particular pixel sensor. The method further includes encoding the pixel events as a function of a tile address, a frame sub-period identifier, and a brightness indicator value.

An optical apparatus captures images of a wide-angle scene with a single camera having a continuous panomorph zoom distortion profile. When combined with a processing unit, the hybrid zoom system creates an output image with constant resolution while allowing continuous adjustment in the magnification and field of view of the image without interpolation like a digital zoom system or without any moving parts like an optical zoom system.

An image sensor includes a pixel array including plural first pixels and a second pixel, and a row decoder configured to supply a second row selection signal to the second pixel and a first pixel that is coupled to the same column line as the second pixel and is accessed simultaneously with the second pixel in a binning mode, and supply a first row selection signal to a remaining first pixel.

A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

An image sensor includes: a plurality of filter units, transmission wavelengths of which can be adjusted; a plurality of photoelectric conversion units that receive light transmitted through the filter unit; and a control unit that alters a size of a first region containing a first filter unit, among the plurality of filter units, through which light at a first wavelength is transmitted before entering a photoelectric conversion unit.

An information processing apparatus including a specification section specifying, from among a plurality of blocks that are set by dividing pixels included in at least a partial region of a pixel region having a plurality of pixels arrayed therein and each of which includes at least one or more of the pixels, at least one or more of the blocks, and a generation section generating a unique value based on pixel values of the pixels included in the specified blocks.

Embodiments relate to image signal processors (ISP) that include binner circuits that down-sample an input image. An input image may include a plurality of pixels. The output image of the binner circuit may include a reduced number of pixels. The binner circuit may include a plurality of different operation modes. In a bin mode, the binner circuit may blend a subset of input pixel values to generate an output pixel quad. In a skip mode, the binner circuit may select one of the input pixel values as the output pixel pixel. The selection may be performed randomly to avoid aliasing. In a luminance mode, the binner circuit may take a weighted average of a subset of pixel values having different colors. In a color value mode, the binner circuit may select one of the colors in a subset of pixel values as an output pixel value.

Systems and methods for a lower energy/faster time of flight camera system configured to measure distance to an object. The system is configured to emit laser light modulated with a first frequency and image light reflected by an object in order to determine a first phase difference between the emitted and reflected light. The system emits laser light modulated with a second frequency and images light reflected by the object to determine a second phase difference between the emitted and reflected light. The distance to the object is determined using the first and second phase differences. The system is arranged to operate at lower energy for obtaining the first phase difference compared with the operation to obtain the second phase difference. This results in lower overall energy consumption and faster overall operation without any significant reduction in accuracy of imaging.

A matrix-array detector includes a set of pixels that are sensitive to a physical effect and arranged in a matrix array in at least one row and columns, each pixel generating a signal dependent on the physical effect, Q column conductors, each connecting the one or more pixels of one and the same column and intended to transport the signals generated by the pixels. The detector further comprises N multiplexers configured to operate simultaneously, each multiplexer receiving the signals from K column conductors, K being greater than or equal to 2, Q being at least equal to K.sup.2. The columns and associated conductors are ordered according to their physical distribution, q representing a current column. The N multiplexers are ordered from 1 to Q/K, n representing the rank of the current multiplexer. The column of rank q, where q is between 1 and K.sup.2, is connected to the multiplexer of rank n=q modulo K. Downstream of the multiplexers, the detector comprises a network of switches allowing signals present at the outputs of the multiplexers to be mixed.