In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

A method of manufacturing a semiconductor device includes forming a first trench in a semiconductor substrate from a first side, forming a semiconductor layer adjoining the semiconductor substrate at the first side, the semiconductor layer capping the first trench at the first side, and forming a contact at a second side of the semiconductor substrate opposite to the first side.

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field effect transistor, a body drive stage to manufacture the body region of the power field effect transistor is shortened to obtain a relatively low on resistance for the power field effect transistor. Before the implanting stage of the dopants of the body region, a pre body drive stage is introduced. During the pre body drive stage and the body drive stage sidewalls of a polysilicon layer of the power field effect transistor are oxidized to obtain a power field effect transistor which has at the sidewalls an oxidized polysilicon layer that is thick enough to prevent a premature current injection from the gate to the source regions of the power field effect transistor.

A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate.

Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

An n.sup. drift layer is a parallel pn layer having an n-type region and a p-type region are alternately arranged in the direction parallel to the main surface so as to come into contact with each other, and have a width in a direction parallel to the main surface of the substrate which is less than a length in a direction perpendicular to the main surface of the substrate. A second-main-surface-side lower end portion of the p-type region has a structure in which a high-concentration lower end portion and a low-concentration lower end portion of a p-type low-concentration region are repeated at a predetermined pitch in the direction parallel to the main surface of the substrate. It is possible to provide a super junction MOS semiconductor device which can improve a trade-off relationship between turn-off loss and turn-off dv/dt and improve avalanche resistance.

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.

A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped P type columns, a floating ring-shaped P type column that surrounds the set of strip-shaped P type columns, and a set of ring-shaped P type columns that surrounds the floating ring-shaped P type column. A source metal is disposed above portions of the charge compensation region. The source metal contacts each of the strip-shaped P type columns and each of the ring-shaped P type columns. An oxide is disposed between the floating P type column and the source metal such that the floating P type column is electrically isolated from the source metal. The device exhibits a breakdown voltage that is 0.2% greater than if the floating P type column were to contact the source metal.