A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element.

Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region. Trenches formed in the first surface include a gate trench and a boundary trench disposed between the gate trench and the diode region. A fourth layer of the semiconductor substrate is provided on the first surface and has a portion included in the diode region. The fourth layer includes a trench-covering well region that covers the deepest part of the boundary trench, a plurality of isolated well regions, and a diffusion region that connects the trench-covering well region and the isolated well regions. The diffusion region has a lower impurity concentration than that of the isolated well regions. A first electrode is in contact with the isolated well regions and away from the diffusion region.

This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.

A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.

A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.

Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices.

In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region.

A semiconductor device is provided that includes a silicon semiconductor body having a drift or base zone of net n-type doping. An n-type doping is partially compensated by 10% to 80% with p-type dopants. A net n-type doping concentration in the drift or base zone is in a range from 110.sup.13 cm.sup.3 to 110.sup.15 cm.sup.3. A portion of 5% to 75% of the n-type doping is made up of hydrogen related donors.